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S6J3120 series 32 - bit traveo? family microcontroller datasheet cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04863 rev.*d revised december 15, 2016 this section provides an overview of the s6j31 2 0 series. the s6j31 2 0 series is a set of 32 - bit microcontrollers designed for in - vehicle use. it uses the arm ? cortex - r5 cpu as a cpu. f eatures this section explains the features of the s6j31 2 0 series. cortex - r5 core ? this section explains the cortex - r5 cpu core. ? arm ? cortex ? - r5 ? 32 - bit arm architecture ? 2 - instruction issuance super scalar ? 8 - stage pipeline ? armv7/thumb ? - 2 instruction set ? mpu (memory protection) equipped ? 16 - area support ? ecc support for the tcm ports for ram 1 - bit error correction and 2 - bit error detection (sec - ded) ? tcm ports 2 tcm ports ? atcm port ? btcm port (b0tcm, b1tcm) ? caches ? instruction cache 16 kb ? data cache 16 kb ? vic port low latency interrupt ? axi master interface 64 - bit axi interface (instruction/data access) 32 - bit axi interface (i/o access) ? axi slave interface 64 - bit axi interface (tc m port access) ? etm - r5 trace peripheral functions this section explains peripheral functions. ? clock generation ? main clock oscillation (4 mhz) ? no sub clock oscillation ? cr oscillation (100 khz) ? cr oscillation (4 mhz) ? built - in flash memory size ? program: 1024 k + 64 kb (s6j312ah z c * ) /768 k + 64 kb (s6j312 9 h z c * ) /512 k + 64 kb (s6j312 8 h z c * ) ? *z: a/b ? work: 112 kb (s6j312ah zc * ) / 112 kb (s6j312 9 h z c * ) / 112 kb (s6j312 8 h zc * ) ? *z: a/b ? built - in ram size ? tcram 64 kb(s6j312ah zc * ) / 48 kb(s6j312 9 h zc * ) /32 kb(s6j312 8 h zc * ) ? system s ram 16 kb (s6j312ah zc * ) / 16 kb (s6j312 9 h zc * ) / 16 kb (s6j312 8 h zc * ) ? backup ram 8 kb (s6j312ah zc * ) / 8 kb (s6j312 9 h zc * ) / 8 kb (s6j312 8 h zc * ) ? *z: a/b ? general - purpose ports: 112 channels (s6j312ah zc * ) / 112 channels (s6j312 9 h zc * ) / 112 channels (s6j312 8 h zc * ) ? *z: a/b ? external bus interface ? 24 - bit address, 16bit data ? dma controller ? up to 16 channels can be activated simultaneously. ? a/d converter (successive approximation type) ? 12 - bit resolution, 2 units mounted: max 50 channels ( 2 2 channels + 2 8 channels) ( s6j312ah zc *)/ max 50 channels ( 2 2 channels + 2 8 channels) ( s6j312 9 h zc *)/ max 50 channels ( 2 2 channels + 2 8 channels) ( s6j312 8 h zc *) ? *z: a/b ? external interrupt input: 16 channels ? level ("h"/"l") and edge (rising/falling) can be detected. ? multi - function serial (transmiss ion and reception fifos mounted) :max 10 channels ( s6j312ah z c *)/ max 10 channels ( s6j312 9 h zc *)/ max 10 channels ( s6j312 8 h zc *) ? *z: a/b < i 2 c > ? full duplex, double buffering system; 64 - byte transmission fifo, 64 - byte reception fifo ? standard mode (max. 100kbps) is supported only. ? dma transfer is supported. ? full duplex, double buffering system; 64 - byte transmission fifo, 64 - byte reception fifo ? parity check can be enabled/disabled. ? built - in dedicated baud rate generator ? an ex ternal clock can be used as a transfer clock. ? parity, frame, overrun error detection functions are available. ? dma transfer is supported.
document number: 002 - 04863 rev.*d page 2 of 141 s6j31 2 0 series ? full duplex, double buffering system; 64 - byte transmission fifo, 64 - byte recep tion fifo ? support for spi. both master and slave roles are supported. data length in bits can be set to a value from 5 to 16 or one of the values of 20, 24, and 32. ? built - in dedicated baud rate generator (master operation) ? external clock input is enabled ( slave operation). ? overrun error detection function is available. ? dma transfer is supported. ? serial chip select spi function ? full duplex, double buffering system; 64 - byte transmission fifo, 64 - byte reception fifo ? support for lin protocol revision 2.1 ? both master and slave roles are supported. ? framing error and overrun error detection ? lin synch break generation and detection, lin synch delimiter generation ? built - in dedicated baud rate generator ? the ex ternal clock can be adjusted by the reload counter. ? dma transfer is supported. ? can controller: can - fd max 3 channel ? can - fd (v3.2.0) ? can transfer speed : 5 mbps ? can clock :max 40mhz ? 192 message buffers/channel (reception message buffer size) ? 32 message buffe r/channel (transmission message buffer size ) ? base timer: max 30 channels ? 16bit timer. ? it is selectable by 4 functions of the pwm/ppg/pwc/reload timer. ? 2 - channel cascade connection enables operation as a 32 - bit timer.(pwc and reload timer) ? reload timer: max 10 channels ? 32bit timer. ? free - run timer: max 6 channels ? 32bit timer. ? main clock oscillation and cr oscillation are available. ? free - run timer output can work in combination with an input capture and an output compare. ? input capture: max 12 channels ? 32bit timer. ? output compare: max 12 channels ? 32bit timer. ? sound generator : max 3 channels ? frequency and amplitude sequencers provide d . ? stepping motor controller : max 4 channels ? 8/10 - bit pwm ? high current output supported (4 lines 4 channels) ? can refer back el ectromotive force using pin - shared a/d converter ? lcd controller ? common output : 4 , segment output : 32 ? duty drive (seg0 to seg31) and static drive (st0 to st8) can be switched. ? each of com0 to com3, seg0 to seg31, v0, v1, v2, and v3 pins for duty drive ca n be switched to the general - purpose port. (the seg23 to seg31 pins can be switched to static driving.) ? v0, v1, v2 and v3 pin can be used as the general - purpose port. but v3 pin cannot be used as an output pin. ? each of st0 to st8 pins for static drive can be switched to the general - purpose port, or it can be switched to the segment output of duty drive. ? quad position & revolution counter(qprc) : max 2 channels ? real time clock (rtc) (day/hour/minute/second) ? main clock oscillation or cr oscillation (100 khz) can be selected as an operation clock. ? calibration: real time clock (rtc) driven by the cr clock ? correction can be done by configuring the prescaler of the real time clock based on the ratio between the main clock and the cr clock. ? clock supervisor ? abnorma lity (such as damaged crystal) of the main clock oscillation (4 mhz) can be monitored. ? the clock can switch to the cr clock when an abnormality is detected. ? pll abnormality can be detected. ? crc generation ? fixed - length crc ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 ? ddr hs - spi ? e 2 prom and the flash device of the single/dual/quad - spi protocol can be connected. ? watchdog timer ? hardware watchdog ? software watchdog ? nmi ? i/o relocation ? peripheral function pin locations can be changed. ? low - power consumption control ? standby function ? power - off function ? partial wakeup function ? power - on reset ? low - voltage detection reset ? security ? flash security ? interface security (jtag + test port) ? she ? unique device id ? package: leu144 (s6j312x hz c *) ? *x:a/9/8, z: a/b ? cmos 55 nm technology
document number: 002 - 04863 rev.*d page 3 of 141 s6j31 2 0 series ? power supply ? 5 v single power supply ? the voltage step - down circuit generates internal 1.2 v from 5 v. ? 5 v power supply is used for i/o.
document number: 002 - 04863 rev.*d page 4 of 141 s6j31 2 0 series table of contents features ................................ ................................ ................................ ................................ ................................ ................... 1 1. p roduct lineup ................................ ................................ ................................ ................................ ................................ .. 6 2. pin assignment ................................ ................................ ................................ ................................ ................................ . 8 3. pin description ................................ ................................ ................................ ................................ ................................ .. 9 4. i/o cir cuit types ................................ ................................ ................................ ................................ .............................. 27 5. handling precautions ................................ ................................ ................................ ................................ ..................... 31 5.1 precautions for product design ................................ ................................ ................................ ................................ ... 31 5.2 precautions for package mounting ................................ ................................ ................................ .............................. 33 5.3 precautions for use environment ................................ ................................ ................................ ................................ 35 6. handling devices ................................ ................................ ................................ ................................ ............................ 36 7. block diagram ................................ ................................ ................................ ................................ ................................ . 39 8. memory map ................................ ................................ ................................ ................................ ................................ .... 40 9. pin statuse s in cpu status ................................ ................................ ................................ ................................ ............ 46 10. electrical characteristics ................................ ................................ ................................ ................................ ............... 50 10.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 50 10.2 recommended operating conditions ................................ ................................ ................................ .......................... 52 10.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 55 10.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 67 10.4.1 source clock timing ................................ ................................ ................................ ................................ .................... 67 10.4.2 internal clock timing ................................ ................................ ................................ ................................ ................... 69 10.4.3 reset input ................................ ................................ ................................ ................................ ................................ ... 73 10.4.4 power - on conditions ................................ ................................ ................................ ................................ .................... 74 10.4.5 clock output timing ................................ ................................ ................................ ................................ ..................... 75 10.4.6 external bus interface timing ................................ ................................ ................................ ................................ ...... 76 10.4.6.1 common timing between read and write ................................ ................................ ................................ ............ 76 10.4.6.2 read timing ................................ ................................ ................................ ................................ ........................... 77 10.4.6.3 write timing ................................ ................................ ................................ ................................ ........................... 78 10.4.7 multi - function serial ................................ ................................ ................................ ................................ .................... 79 10.4.7.1 csio timing (smr:md[2:0]=010 b ) ................................ ................................ ................................ ........................ 79 10.4.7.2 uart (async serial interface) timing (smr:md[2:0]=000 b , 001 b ) ................................ ................................ ..... 99 10.4.7.3 lin interface (v2.1) (lin communication control interface (v2.1)) timing (smr:md[2:0]=011 b ) ........................ 100 10.4.7.4 i 2 c timing (smr:md[2:0]=100b) ................................ ................................ ................................ ......................... 101 10.4.8 hs - spi timing ................................ ................................ ................................ ................................ ........................... 103 10.4.8.1 sdr mode timing ................................ ................................ ................................ ................................ ................ 103 10.4.8.2 ddr mode timing ................................ ................................ ................................ ................................ ............... 105 10.4.9 high current output slew rate ................................ ................................ ................................ ................................ .. 107 10.5 timer input timing ................................ ................................ ................................ ................................ ..................... 108 10.6 qprc timing ................................ ................................ ................................ ................................ ............................ 109 10.7 trigger input timing ................................ ................................ ................................ ................................ .................. 112 10.8 nmi input timing ................................ ................................ ................................ ................................ ....................... 113 10.9 low - voltage detection (external low - voltage detection) ................................ ................................ ......................... 114
document number: 002 - 04863 rev.*d page 5 of 141 s6j31 2 0 series 10.10 low - voltage detection (ram retention low - voltage detection) ................................ ................................ .............. 115 10.11 low - voltage detection (1.2 v power supply low - voltage detection) ................................ ................................ ....... 115 10.12 a/d converter ................................ ................................ ................................ ................................ ............................ 117 10.12.1 electrical characteristics ................................ ................................ ................................ ................................ ........ 117 10.12.2 notes on using a/d converters ................................ ................................ ................................ .............................. 119 10.12.3 definition of terms ................................ ................................ ................................ ................................ .................. 120 10.13 flash memory ................................ ................................ ................................ ................................ ............................ 122 11. orde ring information ................................ ................................ ................................ ................................ .................... 123 12. part number option ................................ ................................ ................................ ................................ ...................... 123 13. package dimensions ................................ ................................ ................................ ................................ .................... 124 14. appendix ................................ ................................ ................................ ................................ ................................ ........ 125 14.1 application 1: jtag tool connection ................................ ................................ ................................ .......................... 125 15. major changes ................................ ................................ ................................ ................................ .............................. 126 document h istory ................................ ................................ ................................ ................................ ............................... 139 sales, solutions, and legal information ................................ ................................ ................................ ........................... 141
document number: 002 - 04863 rev.*d page 6 of 141 s6j31 2 0 series 1. p roduct l ineup the following table lists the product lineup of the s6j31 2 0 series. table 3 - 1 memory size s6j312ahz c * s6j3129hz c * s6j3128hz c * flash program 1024k bytes + small sector (8 kb x 8) 768k bytes + small sector (8 kb x 8) 512k bytes + small sector (8 kb x 8) work 112k bytes 112k bytes 112k bytes ram tcram 64k bytes 48k bytes 32k bytes system sram 16k bytes 16k bytes 16k bytes backup ram 8k bytes 8k bytes 8k bytes *z: a/b table 3 - 2 she option s6j31 2 xha c * s6j31 2 xhb c * security (she) on off * x: a/9/8 table 3 - 3 : product lineup s6j31 2xhz c * 1 cpu core coretex - r5 cmos 55 nm technology 55 nm package leu144 main clock 4 mhz built - in cr oscillator 100 khz 4 mhz maximum cpu operating frequency 1 2 8 mhz watchdog timer 1 channel (hardware) 1 channel (software) clock supervisor yes external power supply, low - voltage detection reset yes internal power supply, low - voltage detection reset yes nmi request yes external interrupt 16 channels dma controller 16 channels can - fd 3 channels (192 msg buffers/ch)
document number: 002 - 04863 rev.*d page 7 of 141 s6j31 2 0 series s6j31 2xhz c * 1 multi - function serial 10 channels * 2 a/d converter 12 - bit (2 units) unit 0 x 22 channels unit 1 x 28 channels free - run timer 6 channels input capture 12 channels output compare 12 channels base timer (16 - bit) 30 channels real time clock (rtc) 1 channel cr clock calibration yes crc generation yes low - power consumption mode standby function power - off function partial wakeup function she yes external bus i/f address : 24 - bit data :16 - bit reload timer(32bit) 10 channels quad position & revolution counter 2 channels ddr hs - spi yes lcd controller 32seg x 4com(static drive 8seg x 1com) sound generator 3 channels stepping motor controller 4 channels general - purpose port gpio 1 12 channels power supply 5 v 10% operation assurance temperature (ta) - 40 c to +1 0 5 c on - chip debugger (jtag) yes * 1 : x: a / 9 / 8, z: a/b * 2 : i 2 c - uart function is not supported at multi - function serial ch.1, ch.2, and ch.12.
document number: 002 - 04863 rev.*d page 8 of 141 s6j31 2 0 series 2. p in a ssignment the following figures show the pin assignment of the s6j31 2 0 series. figure 4 - 1 pin assignment for s6j312 x h zc * * x: a/9/8, z: a/b vcc p421/int12_1/sin2_1/tracectl/mad01/seg7 p420/sck2_1/traceclk/mad02/seg6 p418/int14_0/scs22_0/tiob23_0/tot33/mad03/seg5 p417/int15_1/sot10_1/tioa23_1/tin33/mad04/seg4 p416/sin10_1/in5_0/tioa22_1/tot32/mad05/seg3 p414/scs21_0/tin32/mad06/seg2 p413/int14_1/scs20_0/scs103_1/tot19/mad07/seg1 p409/sot2_0/tioa24_1/tracedata6/tot18/mad09/com3 p408/sin2_0/tracedata5/tin18/mad10/com2 p407/sck12_0/sck10_1/tracedata4/mad11/com1 p406/sot12_0/tracedata3/mad12/com0/sgo2_1 p405/int11_0/sin12_0/in4_0/tracedata2/mad13/v0/sga2_1 p404/scs120_0/in3_0/tracedata1/mad14/v1/sgo1_1 p403/in2_0/tracedata0/v2/sga1_1 p402/int2_0/rx1_0/in1_0/v3 p401/tx1_0/in0_0 c vss vcc rstx p400/mcsx2/sgo0_1 p331/mcsx3/sga0_1 vss x1 x0 md nmix p327/wot tck tms tdi/p324 tdo/p323 trst/p322 vcc 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vss 1 108 vss p000/sot2_1/ain8_0/mad00/seg8 2 107 p321/pwutrg p001/scs20_1/bin8_0/mdata15/seg9 3 106 dvss p003/scs22_1/zin8_0/mdata14/seg10 4 105 dvcc p005/sin3_0/in6_0/ain9_0/mdata13/seg11 5 104 p317/int11_1/an62/rx1_1/sin10_0/tiob29_0/tioa9_1/pwm2m3 p006/sot3_0/sda3_0/in7_0/bin9_0/mdata12/seg12 6 103 p315/an61/tx1_1/scs100_0/in5_1/tiob28_0/tioa8_1/pwm2p3 p007/sck3_0/scl3_0/in8_0/zin9_0/mdata11/seg13 7 102 p314/an60/sck10_0/scl10_0/in4_1/tiob27_0/tioa7_1/pwm1m3 p008/scs30_0/in9_0/tioa0_0/mdata10/seg14 8 101 p313/int10_1/an59/sot10_0/sda10_0/in3_1/tiob26_0/pwm1p3 p009/int0_1/sin11_0/in10_0/tioa1_0/mdata09/seg15 9 100 p312/an58/scs101_0/in2_1/tiob25_0/pwm2m2 p010/sot11_0/sda11_0/in11_0/tioa2_0/mdata08/seg16 10 99 p309/an57/in1_1/tioa29_1/pwm2p2 p012/sck11_0/scl11_0/out5_0/tioa3_0/moex/seg17 11 98 p308/an56/in0_1/tioa28_1/pwm1m2 p013/scs110_0/out6_0/tioa4_0/mwex/seg18 12 97 p307/int1_0/an55/scs102_0/tiob18_0/pwm1p2 p015/scs111_0/out7_0/tioa5_0/mcsx0/seg19 13 96 dvss p016/scs112_0/out8_0/tioa6_0/mcsx1/seg20 14 95 dvcc p017/scs113_0/out9_0/tioa7_0/mdqm0/seg21 15 94 p305/an53/text5_0/tioa29_0/pwm2m1 p018/out10_0/tioa8_0/mdqm1/seg22 16 93 p304/an52/text4_0/tioa20_1/pwm2p1 p019/text0_0/out11_0/tiob0_0/mad15/seg23/st0 17 92 p302/an51/tioa19_1/pwm1m1 p020/sot0_0/sda0_0/text1_0/tiob1_0 18 91 p301/an50/out4_0/tioa18_1/pwm1p1 p021/sck0_0/scl0_0/sck4_1/tiob2_0 19 90 p300/an49/out3_0/tioa28_0/pwm2m0 p022/int3_0/sin0_0/tiob3_0 20 89 p231/an48/out2_0/tioa27_0/pwm2p0 p023/scs0_0/sin4_1/tiob4_0/mad16/seg24/st1 21 88 p230/an47/pwu_an7/out1_0/tioa26_0/pwm1m0 p024/sot4_1/tiob5_0/mad17/seg25/st2 22 87 p229/int8_0/an46/pwu_an6/out0_0/tioa25_0/pwm1p0 p027/scs42_1/text0_1/tiob6_0/tioa4_1/mad18/seg26/st3 23 86 dvss p028/sin1_0/out0_1/tiob7_0/mad19/seg27/st4 24 85 dvcc p029/sot1_0/out1_1/mad20/seg28/st5 25 84 avcc1 p030/scs43_1/out2_1/tiob8_0/mad21/seg29/st6 26 83 avrh1 p031/scs1_0/out3_1/mad22/seg30/st7 27 82 avss1/avrl1 p100/sck1_0/out4_1/mad23/seg31/st8 28 81 p226/an43/pwu_an3/sck8_0/scl8_0/in11_2/tioa17_1 p101/an3/out5_1/mdata07 29 80 p225/int0_0/an42/pwu_an2/rx0_2/sot8_0/sda8_0/in10_2/tiob17_0/zin9_1 p103/an5/out6_1/tiob9_0/mdata06 30 79 p224/an41/pwu_an1/tx0_2/scs80_0/in9_2/bin9_1 p105/out7_1/tioa9_0/mdata05 31 78 p223/an40/pwu_an0/scs81_0/in8_2/ain9_1 p106/tx1_2/out8_1/tin0/mdata04 32 77 p222/int7_0/an39/rx2_0/sin8_0/in7_2 p107/int2_1/rx1_2/out9_1/tioa10_0/tot0/mdata03 33 76 p220/an38/tx2_0/scs83_0/in6_2/tiob16_0 p108/int3_1/an6/out10_1/tioa11_0/tin1/mrdy 34 75 p219/an37/text3_0/tiob15_0 p109/out11_1/tioa12_0/tot1/mclk 35 74 p218/an36/text2_0/tiob14_0 vcc 36 73 vss 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vss c p112/an9/tioa13_0/tin2/mdata02 p113/tioa5_1/tot2/mdata01 p114/an10/tioa6_1/tin3/mdata00 avcc0 avrh0 avss0/avrl0 p115/tiob10_0/tot3 p117/int4_1/an12/tiob11_0/tin16 p118/int5_1/an13/tiob12_0/tot16 p119/an14/scs90_0/tiob13_0/tin17 p120/an15/scs91_0/tot17 p122/an17/scs92_0/tioa11_1/sga0_0 p123/an18/scs93_0/tioa12_1/sgo0_0 p126/an19/sga1_0 p127/an20/text1_1/sgo1_0 p128/an21/text2_1/sga2_0 p129/an22/in6_1/sgo2_0 p130/int5_0/an23/sin9_0/in7_1 p131/an24/sot9_0/sda9_0/in8_1 p202/int6_1/sck9_0/scl9_0/in9_1 p203/in10_1/tiob19_0/ain8_1 p204/an27/in11_1/tiob20_0/bin8_1 p205/an28/text3_1/tiob21_0/zin8_1 p206/an29/scs43_0/text4_1/tiob22_0 p207/int7_1/an30/sck4_0/scl4_0/text5_1/spisel3 p208/an31/scs42_0/tioa19_0/spisel2 p209/an32/sot4_0/sda4_0/tioa20_0/spisel1 p210/int6_0/an33/sin4_0/in0_2/tioa21_0/spiclk p211/an34/scs40_0/in1_2/tioa22_0/spidat0 p212/an35/scs41_0/scs80_1/in2_2/tioa13_1/spidat2 p213/int8_1/sin8_1/in3_2/tioa14_1/spidat1 p214/sot8_1/in4_2/tioa15_1/spisel0 p215/int9_1/sck8_1/in5_2/tioa16_1/spidat3 vcc top view leu-144 p411/int13_1/sck2_0/scs101_1/tiob24_0/tracedata7/tin19/mad08/seg0
document number: 002 - 04863 rev.*d page 9 of 141 s6j31 2 0 series 3. p in d escription this section provides a list of the pin functions of the s6j31 2 0 series table 5 - 1 s6j312 x h zc * pin functions * x: a / 9 / 8 , z: a/b pin no. pin name polarity i/o circuit type function 2 p000 sot2_1 ain8_0 mad00 seg8 - - - - - k general - purpose i/o port multi - function serial ch.2 serial data output pin (1) qprc ch.8 ain input pin (0) external bus interface address bit0 output pin lcdc segment 8 (duty) output pin 3 p001 scs20_1 bin8_0 mdata15 seg9 - - - - - k general - purpose i/o port multi - function serial ch.2 serial chip select 0 i/o pin (1) qprc ch.8 bin input pin (0) external bus interface data bus bit15 i/o pin lcdc segment 9 (duty) output pin 4 p003 scs22_1 zin8_0 mdata14 seg10 - - - - - k general - purpose i/o port multi - function serial ch.2 serial chip select 2 output pin (1) qprc ch.8 zin input pin (0) external bus interface data bus bit14 i/o pin lcdc segment 10 (duty) output pin 5 p005 sin3_0 in6_0 ain9_0 mdata13 seg11 - - - - - - k general - purpose i/o port multi - function serial ch.3 serial data input pin (0) input capture ch.6 input pin (0) qprc ch.9 ain input pin (0) external bus interface data bus bit13 i/o pin lcdc segment 11 (duty) output pin 6 p006 sot3_0 sda3_0 in7_0 bin9_0 mdata12 seg12 - - - - - - - k general - purpose i/o port multi - function serial ch.3 serial data output pin (0) i 2 c bus ch.3 serial data i/o pin input capture ch.7 input pin (0) qprc ch.9 bin input pin (0) external bus interface data bus bit12 i/o pin lcdc segment 12 (duty) output pin 7 p007 sck3_0 scl3_0 in8_0 zin9_0 mdata11 seg13 - - - - - - - k general - purpose i/o port multi - function serial ch.3 clock i/o pin (0) i 2 c bus ch.3 serial clock i/o pin input capture ch.8 input pin (0) qprc ch.9 zin input pin (0) external bus interface data bus bit11 i/o pin lcdc segment 13 (duty) output pin
document number: 002 - 04863 rev.*d page 10 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 8 p008 scs30_0 in9_0 tioa0_0 mdata10 seg14 - - - - - - k general - purpose i/o port multi - function serial ch.3 serial chip select 0 i/o pin (0) input capture ch.9 input pin (0) base timer ch.0 tioa output pin (0) external bus interface data bus bit10 i/o pin lcdc segment 14 (duty) output pin 9 p009 int0_1 sin11_0 in10_0 tioa1_0 mdata09 seg15 - - - - - - - k general - purpose i/o port int0 external interrupt input pin (1) multi - function serial ch.11 serial data input pin (0) input capture ch.10 input pin (0) base timer ch.1 tioa i/o pin (0) external bus interface data bus bit9 i/o pin lcdc segment 15 (duty) output pin 10 p010 sot11_0 sda11_0 in11_0 tioa2_0 mdata08 seg16 - - - - - - - k general - purpose i/o port multi - function serial ch.11 serial data output pin (0) i 2 c bus ch.11 serial data i/o pin input capture ch.11 input pin (0) base timer ch.2 tioa output pin (0) external bus interface data bus bit8 i/o pin lcdc segment 16 (duty) ou tput pin 11 p012 sck11_0 scl11_0 out5_0 tioa3_0 moex seg17 - - - - - - - k general - purpose i/o port multi - function serial ch.11 clock i/o pin (0) i 2 c bus ch.11 serial clock i/o pin output compare ch.5 output pin (0) base timer ch.3 tioa i/o pin (0) external bus interface read enable output pin lcdc segment 17 (duty) output pin 12 p013 scs110_0 out6_0 tioa4_0 mwex seg18 - - - - - - k general - purpose i/o port multi - function serial ch.11 serial chip select 0 i/o pin (0) output compare ch.6 output pin (0) base timer ch.4 tioa output pin (0) external bus interface write enable output pin lcdc segment 18 (duty) output pin 13 p015 scs111_0 out7_0 tioa5_0 mcsx0 seg19 - - - - - - k general - purpose i/o port multi - function serial ch.11 serial chip select 1 output pin (0) output compare ch.7 output pin (0) base timer ch.5 tioa i/o pin (0) external bus interface chip select 0 output pin lcdc segment 19 (duty) output pin
document number: 002 - 04863 rev.*d page 11 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 14 p016 scs112_0 out8_0 tioa6_0 mcsx1 seg20 - - - - - - k general - purpose i/o port multi - function serial ch.11 serial chip select 2 output pin (0) output compare ch.8 output pin (0) base timer ch.6 tioa output pin (0) external bus interface chip select 1 output pin lcdc segment 20 (duty) output pin 15 p017 scs113_0 out9_0 tioa7_0 mdq m0 seg21 - - - - - - k general - purpose i/o port multi - function serial ch.11 serial chip select 3 output pin (0) output compare ch.9 output pin (0) base timer ch.7 tioa i/o pin (0) external bus interface byte mask 0 output pin lcdc segment 21 (duty) output pin 16 p018 out10_0 tioa8_0 mdqm1 seg22 - - - - - k general - purpose i/o port output compare ch.10 output pin (0) base timer ch.8 tioa output pin (0) external bus interface byte mask 1 output pin lcdc segment 22 (duty) output pin 17 p019 text0_0 out11_0 tiob0_0 mad15 seg23/st0 - - - - - - k general - purpose i/o port free - run timer 0 clock input pin (0) output compare ch.11 output pin (0) base timer ch.0 tiob input pin (0) external bus interface address bit15 output pin lcdc segment 23 (duty) / segment 0 (static) output pin 18 p020 sot0_0 sda0_0 text1_0 tiob1_0 - - - - - q general - purpose i/o port multi - function serial ch.0 serial data output pin (0) i 2 c bus ch.0 serial data i/o pin free - run timer 1 clock input pin (0) base timer ch.1 tiob input pin (0) 19 p021 sck0_0 scl0_0 sck4_1 tiob2_0 - - - - - q general - purpose i/o port multi - function serial ch.0 clock i/o pin (0) i 2 c bus ch.0 serial clock i/o pin multi - function serial ch.4 clock i/o pin (1) base timer ch.2 tiob input pin (0) 20 p022 int3_0 sin0_0 tiob3_0 - - - - q general - purpose i/o port int3 external interrupt input pin (0) multi - function serial ch.0 serial data input pin (0) base timer ch.3 tiob input pin (0)
document number: 002 - 04863 rev.*d page 12 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 21 p023 scs0_0 sin4_1 tiob4_0 mad16 seg24/st1 - - - - - - k general - purpose i/o port multi - function serial ch.0 serial chip select 0 i/o pin (0) multi - function serial ch.4 serial data input pin (1) base timer ch.4 tiob input pin (0) external bus interface address bit16 output pin lcdc segment 24 (duty) / segment 1 (static) output pin 22 p024 sot4_1 tiob5_0 mad17 seg25/st2 - - - - - k general - purpose i/o port multi - function serial ch.4 serial data output pin (1) base timer ch.5 tiob input pin (0) external bus interface address bit17 output pin lcdc segment 25 (duty) / segment 2 (static) output pin 23 p027 scs42_1 text0_1 tiob6_0 tioa4_1 mad18 seg26/st3 - - - - - - - k general - purpose i/o port multi - function serial ch.4 serial chip select 2 output pin (1) free - run timer 0 clock input pin (1) base timer ch.6 tiob input pin (0) base timer ch.4 tioa output pin (1) external bus interface address bit18 output pin lcdc segment 26 (duty) / segment 3 (static) output pin 24 p028 sin1_0 out0_1 tiob7_0 mad19 seg27/st4 - - - - - - k general - purpose i/o port multi - function serial ch.1 serial data input pin (0) output compare ch.0 output pin (1) base timer ch.7 tiob input pin (0) external bus interface address bit19 output pin lcdc segment 27 (duty) / segment 4 (static) output pin 25 p029 sot1_0 out1_1 mad20 seg28/st5 - - - - - k general - purpose i/o port multi - function serial ch.1 serial data output pin (0) output compare ch.1 output pin (1) external bus interface address bit20 output pin lcdc segment 28 (duty) / segment 5 (static) output pin 26 p030 scs43_1 out2_1 tiob8_0 mad21 seg29/st6 - - - - - - k general - purpose i/o port multi - function serial ch.4 serial chip select 3 output pin (1) output compare ch.2 output pin (1) base timer ch.8 tiob input pin (0) external bus interface address bit21 output pin lcdc segment 29 (duty) / segment 6 (static) output pin 27 p031 scs1_0 out3_1 mad22 seg30/st7 - - - - - k general - purpose i/o port multi - function serial ch.1 serial chip select 0 i/o pin (0) output compare ch.3 output pin (1) external bus interface address bit22 output pin lcdc segment 30 (duty) / segment 7 (static) output pin
document number: 002 - 04863 rev.*d page 13 of 14 1 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 28 p100 sck1_0 out4_1 mad23 seg31/st8 - - - - - k general - purpose i/o port multi - function serial ch.1 clock i/o pin (0) output compare ch.4 output pin (1) external bus interface address bit23 output pin lcdc segment 31 (duty) / segment 8 (static) output pin 29 p101 an3 out5_1 mdata07 - - - - b general - purpose i/o port adc analog 3 input pin output compare ch.5 output pin (1) external bus interface data bit7 i/o pin 30 p103 an5 out6_1 tiob9_0 mdata06 - - - - - b general - purpose i/o port adc analog 5 input pin output compare ch.6 output pin (1) base timer ch.9 tiob input pin (0) external bus interface data bit6 i/o pin 31 p105 out7_1 tioa9_0 mdata05 - - - - q general - purpose i/o port output compare ch.7 output pin (1) base timer ch.9 tioa i/o pin (0) external bus interface data bit5 i/o pin 32 p106 tx1_2 out8_1 tin0 mdata04 - - - - - q general - purpose i/o port can transmission data 1 output pin (2) output compare ch.8 output pin (1) reload timer ch.0 event input pin (0) external bus interface data bit4 i/o pin 33 p107 int2_1 rx1_2 out9_1 tioa10_0 tot0 mdata03 - - - - - - - q general - purpose i/o port int2 external interrupt input pin (1) can reception data 1 input pin (2) output compare ch.9 output pin (1) base timer ch.10 tioa output pin (0) reload timer ch.0 output pin (0) external bus interface data bit3 i/o pin 34 p108 int3_1 an6 out10_1 tioa11_0 tin1 mrdy - - - - - - - b general - purpose i/o port int3 external interrupt input pin (1) adc analog 6 input pin output compare ch.10 output pin (1) base timer ch.11 tioa i/o pin (0) reload timer ch.1 event input pin (0) external bus interface ready input pin
document number: 002 - 04863 rev.*d page 14 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 35 p109 out11_1 tioa12_0 tot1 mclk - - - - - q general - purpose i/o port output compare ch.11 output pin (1) base timer ch.12 tioa output pin (0) reload timer ch.1 output pin (0) external bus interface system clock output pin 39 p112 an9 tioa13_0 tin2 mdata02 - - - - - b general - purpose i/o port adc analog 9 input pin base timer ch.13 tioa i/o pin (0) reload timer ch.2 event input pin (0) external bus interface data bit2 i/o pin 40 p113 tioa5_1 tot2 mdata01 - - - - q general - purpose i/o port base timer ch.5 tioa i/o pin (1) reload timer ch.2 output pin (0) external bus interface data bit1 i/o pin 41 p114 an10 tioa6_1 tin3 mdata00 - - - - - b general - purpose i/o port adc analog 10 input pin base timer ch.6 tioa output pin (1) reload timer ch.3 event input pin (0) external bus interface data bit0 i/o pin 45 p115 tiob10_0 tot3 - - - q general - purpose i/o port base timer ch.10 tiob input pin (0) reload timer ch.3 output pin (0) 46 p117 int4_1 an12 tiob11_0 tin16 - - - - - b general - purpose i/o port int4 external interrupt input pin (1) adc analog 12 input pin base timer ch.11 tiob input pin (0) reload timer ch.16 event input pin (0) 47 p118 int5_1 an13 tiob12_0 tot16 - - - - - b general - purpose i/o port int5 external interrupt input pin (1) adc analog 13 input pin base timer ch.12 tiob input pin (0) reload timer ch.16 output pin (0) 48 p119 an14 scs90_0 tiob13_0 tin17 - - - - - b general - purpose i/o port adc analog 14 input pin multi - function serial ch.9 serial chip select 0 i/o pin (0) base timer ch.13 tiob input pin (0) reload timer ch.17 event input pin (0)
document number: 002 - 04863 rev.*d page 15 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 49 p120 an15 scs91_0 tot17 - - - - b general - purpose i/o port adc analog 15 input pin multi - function serial ch.9 serial chip select 1 output pin (0) reload timer ch.17 output pin (0) 50 p122 an17 scs92_0 tioa11_1 sga0_0 - - - - - b general - purpose i/o port adc analog 17 input pin multi - function serial ch.9 serial chip select 2 output pin (0) base timer ch.11 tioa i/o pin (1) sound generator ch.0 sga output pin (0) 51 p123 an18 scs93_0 tioa12_1 sgo0_0 - - - - - b general - purpose i/o port adc analog 18 input pin multi - function serial ch.9 serial chip select 3 output pin (0) base timer ch.12 tioa output pin (1) sound generator ch.0 sgo output pin (0) 52 p126 an19 sga1_0 - - - b general - purpose i/o port adc analog 19 input pin sound generator ch.1 sga output pin (0) 53 p127 an20 text1_1 sgo1_0 - - - - b general - purpose i/o port adc analog 20 input pin free - run timer 1 clock input pin (1) sound generator ch.1 sgo output pin (0) 54 p128 an21 text2_1 sga2_0 - - - - b general - purpose i/o port adc analog 21 input pin free - run timer 2 clock input pin (1) sound generator ch.2 sga output pin (0) 55 p129 an22 in6_1 sgo2_0 - - - - b general - purpose i/o port adc analog 22 input pin input capture ch.6 input pin (1) sound generator ch.2 sgo output pin (0) 56 p130 int5_0 an23 sin9_0 in7_1 - - - - - b general - purpose i/o port int5 external interrupt input pin (0) adc analog 23 input pin multi - function serial ch.9 serial data input pin (0) input capture ch.7 input pin (1) 57 p131 an24 sot9_0 sda9_0 in8_1 - - - - - b general - purpose i/o port adc analog 24 input pin multi - function serial ch.9 serial data output pin (0) i 2 c bus ch.9 serial data i/o pin input capture ch.8 input pin (1)
document number: 002 - 04863 rev.*d page 16 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 58 p202 int6_1 sck9_0 scl9_0 in9_1 - - - - - q general - purpose i/o port int6 external interrupt input pin (1) multi - function serial ch.9 clock i/o pin (0) i 2 c bus ch.9 serial clock i/o pin input capture ch.9 input pin (1) 59 p203 in10_1 tiob19_0 ain8_1 - - - - q general - purpose i/o port input capture ch.10 input pin (1) base timer ch.19 tiob input pin (0) qprc ch.8 ain input pin (1) 60 p204 an27 in11_1 tiob20_0 bin8_1 - - - - - b general - purpose i/o port adc analog 27 input pin input capture ch.11 input pin (1) base timer ch.20 tiob input pin (0) qprc ch.8 bin input pin (1) 61 p205 an28 text3_1 tiob21_0 zin8_1 - - - - - b general - purpose i/o port adc analog 28 input pin free - run timer 3 clock input pin (1) base timer ch.21 tiob input pin (0) qprc ch.8 zin input pin (1) 62 p206 an29 scs43_0 text4_1 tiob22_0 - - - - - b general - purpose i/o port adc analog 29 input pin multi - function serial ch.4 serial chip select 3 output pin (0) free - run timer 4 clock input pin (1) base timer ch.22 tiob input pin (0) 63 p207 int7_1 an30 sck4_0 scl4_0 text5_1 spisel3 - - - - - - - b general - purpose i/o port int7 external interrupt input pin (1) adc analog 30 input pin multi - function serial ch.4 clock i/o pin (0) i 2 c bus ch.4 serial clock i/o pin free - run timer 5 clock input pin (1) hs - spi slave select 3 output pin 64 p208 an31 scs42_0 tioa19_0 spisel2 - - - - - b general - purpose i/o port adc analog 31 input pin multi - function serial ch.4 serial chip select 2 output pin (0) base timer ch.19 tioa i/o pin (0) hs - spi slave select 2 output pin
document number: 002 - 04863 rev.*d page 17 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 65 p209 an32 sot4_0 sda4_0 tioa20_0 spisel1 - - - - - - b general - purpose i/o port adc analog 32 input pin multi - function serial ch.4 serial data output pin (0) i 2 c bus ch.4 serial data i/o pin base timer ch.20 tioa output pin (0) hs - spi slave select 1 output pin 66 p210 int6_0 an33 sin4_0 in0_2 tioa21_0 spiclk - - - - - - - b general - purpose i/o port int6 external interrupt input pin (0) adc analog 33 input pin multi - function serial ch.4 serial data input pin (0) input capture ch.0 input pin (2) base timer ch.21 tioa i/o pin (0) hs - spi clock output pin 67 p211 an34 scs40_0 in1_2 tioa22_0 spidat0 - - - - - - b general - purpose i/o port adc analog 34 input pin multi - function serial ch.4 serial chip select 0 i/o pin (0) input capture ch.1 input pin (2) base timer ch.22 tioa output pin (0) hs - spi data 0 i/o pin 68 p212 an35 scs41_0 scs80_1 in2_2 tioa13_1 spidat2 - - - - - - - b general - purpose i/o port adc analog 35 input pin multi - function serial ch.4 serial chip select 1 output pin (0) multi - function serial ch.8 serial chip select 0 i/o pin (1) input capture ch.2 input pin (2) base timer ch.13 tioa i/o pin (1) hs - spi data 2 i/o pin 69 p213 int8_1 sin8_1 in3_2 tioa14_1 spidat1 - - - - - - q general - purpose i/o port int8 external interrupt input pin (1) multi - function serial ch.8 serial data input pin (1) input capture ch.3 input pin (2) base timer ch.14 tioa output pin (1) hs - spi data 1 i/o pin 70 p214 sot8_1 in4_2 tioa15_1 spisel0 - - - - - q general - purpose i/o port multi - function serial ch.8 serial data output pin (1) input capture ch.4 input pin (2) base timer ch.15 tioa i/o pin (1) hs - spi slave select 0 output pin
document number: 002 - 04863 rev.*d page 18 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 71 p215 int9_1 sck8_1 in5_2 tioa16_1 spidat3 - - - - - - q general - purpose i/o port int9 external interrupt input pin (1) multi - function serial ch.8 clock i/o pin (1) input capture ch.5 input pin (2) base timer ch.16 tioa output pin (1) hs - spi data 3 i/o pin 74 p218 an36 text2_0 tiob14_0 - - - - b general - purpose i/o port adc analog 36 input pin free - run timer 2 clock input pin (0) base timer ch.14 tiob input pin (0) 75 p219 an37 text3_0 tiob15_0 - - - - b general - purpose i/o port adc analog 37 input pin free - run timer 3 clock input pin (0) base timer ch.15 tiob input pin (0) 76 p220 an38 tx2_0 scs83_0 in6_2 tiob16_0 - - - - - - b general - purpose i/o port adc analog 38 input pin can transmission data 2 output pin (0) multi - function serial ch.8 serial chip select 3 output pin (0) input capture ch.6 input pin (2) base timer ch.16 tiob input pin (0) 77 p222 int7_0 an39 rx2_0 sin8_0 in7_2 - - - - - - b general - purpose i/o port int7 external interrupt input pin (0) adc analog 39 input pin can reception data 2 input pin (0) multi - function serial ch.8 serial data input pin (0) input capture ch.7 input pin (2) 78 p223 an40 pwu_an0 scs81_0 in8_2 ain9_1 - - - - - - b general - purpose i/o port adc analog 40 input pin partial wakeup adc analog 0 input pin multi - function serial ch.8 serial chip select 1 output pin (0) input capture ch.8 input pin (2) qprc ch.9 ain input pin (1) 79 p224 an41 pwu_an1 tx0_2 scs80_0 in9_2 bin9_1 - - - - - - - b general - purpose i/o port adc analog 41 input pin partial wakeup adc analog 1 input pin can transmission data 0 output pin (2) multi - function serial ch.8 serial chip select 0 i/o pin (0) input capture ch.9 input pin (2) qprc ch.9 bin input pin (1)
document number: 002 - 04863 rev.*d page 19 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 80 p225 int0_0 pwu_an2 an42 rx0_2 sot8_0 sda8_0 in10_2 tiob17_0 zin9_1 - - - - - - - - - - b general - purpose i/o port int0 external interrupt input pin (0) partial wakeup adc analog 2 input pin adc analog 42 input pin can reception data 0 input pin (2) multi - function serial ch.8 serial data output pin (0) i 2 c bus ch.8 serial data i/o pin input capture ch.10 input pin (2) base timer ch.17 tiob input pin (0) qprc ch.9 zin input pin (1) 81 p226 an43 pwu_an3 sck8_0 scl8_0 in11_2 tioa17_1 - - - - - - - b general - purpose i/o port adc analog 43 input pin partial wakeup adc analog 3 input pin multi - function serial ch.8 clock i/o pin (0) i 2 c bus ch.8 serial clock i/o pin input capture ch.11 input pin (2) base timer ch.17 tioa i/o pin (1) 87 p229 int8_0 an46 pwu_an6 out0_0 tioa25_0 pwm1p0 - - - - - - - m general - purpose i/o port int8 external interrupt input pin (0) adc analog 46 input pin partial wakeup adc analog 6 input pin output compare ch.0 output pin (0) base timer ch.25 tioa i/o pin (0) smc ch.0 (p1) output pin 88 p230 an47 pwu_an7 out1_0 tioa26_0 pwm1m0 - - - - - - m general - purpose i/o port adc analog 47 input pin partial wakeup adc analog 7 input pin output compare ch.1 output pin (0) base timer ch.26 tioa output pin (0) smc ch.0 (m1) output pin 89 p231 an48 out2_0 tioa27_0 pwm2p0 - - - - - m general - purpose i/o port adc analog 48 input pin output compare ch.2 output pin (0) base timer ch.27 tioa i/o pin (0) smc ch.0 (p2) output pin 90 p300 an49 out3_0 tioa28_0 pwm2m0 - - - - - m general - purpose i/o port adc analog 49 input pin output compare ch.3 output pin (0) base timer ch.28 tioa output pin (0) smc ch.0 (m2) output pin
document number: 002 - 04863 rev.*d page 20 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 91 p301 an50 out4_0 tioa18_1 pwm1p1 - - - - - m general - purpose i/o port adc analog 50 input pin output compare ch.4 output pin (0) base timer ch.18 tioa output pin (1) smc ch.1 (p1) output pin 92 p302 an51 tioa19_1 pwm1m1 - - - - m general - purpose i/o port adc analog 51 input pin base timer ch.19 tioa i/o pin (1) smc ch.1 (m1) output pin 93 p304 an52 text4_0 tioa20_1 pwm2p1 - - - - - m general - purpose i/o port adc analog 52 input pin free - run timer 4 clock input pin (0) base timer ch.20 tioa output pin (1) smc ch.1 (p2) output pin 94 p305 an53 text5_0 tioa29_0 pwm2m1 - - - - - m general - purpose i/o port adc analog 53 input pin free - run timer 5 clock input pin (0) base timer ch.29 tioa i/o pin (0) smc ch.1 (m2) output pin 97 p307 int1_0 an55 scs102_0 tiob18_0 pwm1p2 - - - - - - m general - purpose i/o port int1 external interrupt input pin (0) adc analog 55 input pin multi - function serial ch.10 serial chip select 2 output pin (0) base timer ch.18 tiob input pin (0) smc ch.2 (p1) output pin 98 p308 an56 in0_1 tioa28_1 pwm1m2 - - - - - m general - purpose i/o port adc analog 56 input pin input capture ch.0 input pin (1) base timer ch.28 tioa output pin (1) smc ch.2 (m1) output pin 99 p309 an57 in1_1 tioa29_1 pwm2p2 - - - - - m general - purpose i/o port adc analog 57 input pin input capture ch.1 input pin (1) base timer ch.29 tioa i/o pin (1) smc ch.2 (p2) output pin
document number: 002 - 04863 rev.*d page 21 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 100 p312 an58 scs101_0 in2_1 tiob25_0 pwm2m2 - - - - - - m general - purpose i/o port adc analog 58 input pin multi - function serial ch.10 serial chip select 1 output pin (0) input capture ch.2 input pin (1) base timer ch.25 tiob input pin (0) smc ch.2 (m2) output pin 101 p313 int10_1 an59 sot10_0 sda10_0 in3_1 tiob26_0 pwm1p3 - - - - - - - - m general - purpose i/o port int10 external interrupt input pin (1) adc analog 59 input pin multi - function serial ch.10 serial data output pin (0) i 2 c bus ch.10 serial data i/o pin input capture ch.3 input pin (1) base timer ch.26 tiob input pin (0) smc ch.3 (p1) output pin 102 p314 an60 sck10_0 scl10_0 in4_1 tiob27_0 tioa7_1 pwm1m3 - - - - - - - - m general - purpose i/o port adc analog 60 input pin multi - function serial ch.10 clock i/o pin (0) i 2 c bus ch.10 serial clock i/o pin input capture ch.4 input pin (1) base timer ch.27 tiob input pin (0) base timer ch.7 tioa i/o pin (1) smc ch.3 (m1) output pin 103 p315 an61 tx1_1 scs100_0 in5_1 tiob28_0 tioa8_1 pwm2p3 - - - - - - - - m general - purpose i/o port adc analog 61 input pin can transmission data 1 output pin (1) multi - function serial ch.10 serial chip select 0 i/o pin (0) input capture ch.5 input pin (1) base timer ch.28 tiob input pin (0) base timer ch.8 tioa output pin (1) smc ch.3 (p2) output pin 104 p317 int11_1 an62 rx1_1 sin10_0 tiob29_0 tioa9_1 pwm2m3 - - - - - - - - m general - purpose i/o port int11 external interrupt input pin (1) adc analog 62 input pin can reception data 1 input pin (1) multi - function serial ch.10 serial data input pin (0) base timer ch.29 tiob input pin (0) base timer ch.9 tioa i/o pin (1) smc ch. 3 (m2) output pin 107 p321 pwutrg - - r general - purpose output port partial wakeup trigger output pin
document number: 002 - 04863 rev.*d page 22 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 110 trst p322 n - j jtag test reset input pin general - purpose output port 111 tdo p323 - - i jtag test data output pin general - purpose output port 112 tdi p324 - - d jtag test data input pin general - purpose output port 113 tms - e jtag test mode state input pin 114 tck - e jtag test clock input pin 115 p327 wot - - q general - purpose i/o port rtc output pin 116 nmix - f non - maskable interrupt input pin 117 md - c mode pin 118 x0 - g main clock oscillation input pin 119 x1 - g main clock oscillation output pin 121 p331 mcsx3 sga0_1 - - - q general - purpose i/o port external bus interface chip select 3 output pin sound generator ch.0 sga output pin (1) 122 p400 mcsx2 sgo0_1 - - - q general - purpose i/o port external bus interface chip select 2 output pin sound generator ch.0 sgo output pin (1) 123 rstx n f external reset input pin 127 p401 tx1_0 in0_0 - - - q general - purpose i/o port can transmission data 1 output pin (0) input capture ch.0 input pin (0) 128 p402 int2_0 rx1_0 in1_0 v3 - - - - - l general - purpose i/o port (input only. no output.) int2 external interrupt input pin (0) can reception data 1 input pin (0) input capture ch.1 input pin (0) lcdc reference voltage v3 input pin 129 p403 in2_0 tracedata0 v2 sga1_1 - - - - - b general - purpose i/o port input capture ch.2 input pin (0) trace data 0 output pin lcdc reference voltage v2 input pin sound generator ch.1 sga output pin (1)
document number: 002 - 04863 rev.*d page 23 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 130 p404 scs120_0 in3_0 tracedata1 mad14 v1 sgo1_1 - - - - - - - b general - purpose i/o port multi - function serial ch.12 serial chip select 0 i/o pin (0) input capture ch.3 input pin (0) trace data 1 output pin external bus interface address bit14 output pin lcdc reference voltage v1 input pin sound generator ch.1 sgo output pin (1) 131 p405 int11_0 sin12_0 in4_0 tracedata2 mad13 v0 sga2_1 - - - - - - - - b general - purpose i/o port int11 external interrupt input pin (0) multi - function serial ch.12 serial data input pin (0) input capture ch.4 input pin (0) trace data 2 output pin external bus interface address bit13 output pin lcdc reference voltage v0 input pin sound generator ch.2 sga output pin (1) 132 p406 sot12_0 tracedata3 mad12 com0 sgo2_1 - - - - - - k general - purpose i/o port multi - function serial ch.12 serial data output pin (0) trace data 3 output pin external bus interface address bit12 output pin lcdc segment(duty) common 0 output pin sound generator ch.2 sgo output pin (1) 133 p407 sck12_0 sck10_1 tracedata4 mad11 com1 - - - - - - k general - purpose i/o port multi - function serial ch.12 clock i/o pin (0) multi - function serial ch.10 clock i/o pin (1) trace data 4 output pin external bus interface address bit11 output pin lcdc segment(duty) common 1 output pin 134 p408 sin2_0 tracedata5 tin18 mad10 com2 - - - - - - k general - purpose i/o port multi - function serial ch.2 serial data input pin (0) trace data 5 output pin reload timer ch.18 event input pin (0) external bus interface address bit10 output pin lcdc segment(duty) common 2 output pin 135 p409 sot2_0 tioa24_1 tracedata6 tot18 mad09 com3 - - - - - - - k general - purpose i/o port multi - function serial ch.2 serial data output pin (0) base timer ch.24 tioa output pin (1) trace data 6 output pin reload timer ch.18 output pin (0) external bus interface address bit9 output pin lcdc segment(duty) common 3 output pin
document number: 002 - 04863 rev.*d page 24 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 136 p411 int13_1 sck2_0 scs101_1 tiob24_0 tracedata7 tin19 mad08 seg0 - - - - - - - - - k general - purpose i/o port int13 external interrupt input pin (1) multi - function serial ch.2 clock i/o pin (0) multi - function serial ch.10 serial chip select 1 output pin (1) base timer ch.24 tiob input pin (0) trace data 7 output pin reload timer ch.19 event input pin (0) external bus interface address bit8 output pin lcdc segment 0 (duty) output pin 137 p413 int14_1 scs20_0 scs103_1 tot19 mad07 seg1 - - - - - - - k general - purpose i/o port int14 external interrupt input pin (1) multi - function serial ch.2 serial chip select 0 i/o pin (0) multi - function serial ch.10 serial chip select 3 output pin (1) reload timer ch.19 output pin (0) external bus interface address bit7 output pin lcdc segment 1 (duty) output pin 138 p414 scs21_0 tin32 mad06 seg2 - - - - - k general - purpose i/o port multi - function serial ch.2 serial chip select 1 output pin (0) reload timer ch.32 event input pin (0) external bus interface address bit6 output pin lcdc segment 2 (duty) output pin 139 p416 sin10_1 in5_0 tioa22_1 tot32 mad05 seg3 - - - - - - - k general - purpose i/o port multi - function serial ch.10 serial data input pin (1) input capture ch.5 input pin (0) base timer ch.22 tioa output pin (1) reload timer ch.32 output pin (0) external bus interface address bit5 output pin lcdc segment 3 (duty) output pin 140 p417 int15_1 sot10_1 tioa23_1 tin33 mad04 seg4 - - - - - - - k general - purpose i/o port int15 external interrupt input pin (1) multi - function serial ch.10 serial data output pin (1) base timer ch.23 tioa i/o pin (1) reload timer ch.33 event input pin (0) external bus interface address bit4 output pin lcdc segment 4 (duty) output pin
document number: 002 - 04863 rev.*d page 25 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 141 p418 int14_0 scs22_0 tiob23_0 tot33 mad03 seg5 - - - - - - - k general - purpose i/o port int14 external interrupt input pin (0) multi - function serial ch.2 serial chip select 2 output pin (0) base timer ch.23 tiob input pin (0) reload timer ch.33 output pin (0) external bus interface addre ss bit3 output pin lcdc segment 5 (duty) output pin 142 p420 sck2_1 traceclk mad02 seg6 - - - - - k general - purpose i/o port multi - function serial ch.2 clock i/o pin (1) trace clock external bus interface address bit2 output pin lcdc segment 6 (duty) output pin 143 p421 int12_1 sin2_1 tracectl mad01 seg7 - - - - - - k general - purpose i/o port int12 external interrupt input pin (1) multi - function serial ch.2 serial data input pin (1) trace control external bus interface address bit1 output pin lcdc segment 7 (duty) output pin 42 avcc0 - - analog power supply pin for ad converter unit 0 84 avcc1 - - analog power supply pin for ad converter unit 1 43 avrh0 - - upper - limit reference voltage pin for ad converter unit 0 83 avrh1 - - upper - limit reference voltage pin for ad converter unit 1 44 avss0 avrl0 - - - - gnd pin for ad converter unit 0 lower - limit reference voltage pin for ad converter unit 0 82 avss1 avrl1 - - - - gnd pin for ad converter unit 1 lower - limit reference voltage pin for ad converter unit 1 38 c - - external capacity connection output pin 126 36 vcc - - power supply pin 72 109 124 144
document number: 002 - 04863 rev.*d page 26 of 141 s6j31 2 0 series pin no. pin name polarity i/o circuit type function 1 vss - - gnd 37 73 108 120 125 85 dvcc - - power supply pin for smc high current 95 105 86 dvss - - gnd pin for smc high current 96 106
document number: 002 - 04863 rev.*d page 27 of 141 s6j31 2 0 series 4. i/o c ircuit t ypes this section explains i/o circuit types. type circuit overview a ? general - purpose i/o port with analog input ? output of 1 ma or 2 ma selectable ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? cmos hysteresis input b ? general - purpose i/o port with analog input ? output of 1 ma or 2 ma selectable ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? automotive/cmos hysteresis input selectable c ? mode input ? cmos hysteresis input d ? jtag ? general - purpose output port ? output of 2 ma ? 50 k with pull - up resistor control ? ttl input analog input pull - up control digital output digital output cmos input pss control pull - down control analog input pull - up control digital output digital output pss control pull - down control automotive/ cmos input mode input pull - up control digital output digital output ttl input
document number: 002 - 04863 rev.*d page 28 of 141 s6j31 2 0 series type circuit overview e ? jtag ? 50 k with pull - up resistor control ? ttl input f ? cmos hysteresis input ? 50 k with pull - up resistor g ? main oscillation i/o i ? jtag ? output of 2 ma j ? jtag ? general - purpose output port ? output of 2 ma ? 50 k with pull - down resistor control ? ttl input pull - up control ttl input input standby control digital output digital output digital output digital output ttl input pull - down control cmos - hys input
document number: 002 - 04863 rev.*d page 29 of 141 s6j31 2 0 series type circuit overview k ? general - purpose i/o port with com/seg output ? output of 1 ma or 2 ma selectable ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? automotive/cmos hysteresis input selectable l ? general - purpose i/o port with lcdc v3 input ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? automotive/cmos hysteresis input selectable m ? general - purpose i/o port with analog input ? output of 1 ma or 2 ma or 30ma selectable ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? automotive/cmos hysteresis input selectable q ? general - purpose i/o port ? output of 1 ma or 2 ma selectable ? 50 k with pull - up resistor control ? 50 k with pull - down resistor control ? automotive/cmos hysteresis input selectable com/seg out put pull - up control digital output digital output pss control pull - down control automotive/ cmos input lcdc v3 input pull - up control pss control pull - down control automotive/ cmos input analog input pull - up control digital output digital output pss control pull - down control automotive/ cmos input pull - up control digital output digital output pss control pull - down control automotive/ cmos input
document number: 002 - 04863 rev.*d page 30 of 141 s6j31 2 0 series type circuit overview r ? output of 2 ma digital output digital output
document number: 002 - 04863 rev.*d page 31 of 141 s6j31 2 0 series 5. h andling p recautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 5.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolut e maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not excee d these ratings. recommended operating c onditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operat ing conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applica tion outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. (1) preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the de vice. try to prevent such overvoltage or over - current conditions at the design stage. (2) protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditi ons if present for extended periods of time can damage the device. therefore, avoid this type of connection. (3) handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins s hould be connected through an appropriate resistance to a power supply pin or ground pin.
document number: 002 - 04863 rev.*d page 32 of 141 s6j31 2 0 series latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulations and standards most countries in the world have established standards an d regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (com puters, office automation and other office equipment, industrial, communi cations, and measurement equip ment, personal or hou sehold devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may direct ly affect human lives or cause physical injury or property damage, or where extremely high levels of reliabi lity are demanded (such as aerospace systems, atomic energy controls, sea floor re peaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be resp onsible for damages arising from such use without prior approval.
document number: 002 - 04863 rev.*d page 33 of 141 s6j31 2 0 series 5.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress s recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the solderin g process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface tre atment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. surface mount type surface mo unt packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connec tions caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in a ccordance with cypress ranking of recommended conditions. lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where te mperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 ? c and 30 ? c. w hen you open dry package that recommends humidity 40% to 70% relative humidity. (3) whe n necessary, cypress packages semiconduc tor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 ? c/24 h
document number: 002 - 04863 rev.*d page 34 of 141 s6j31 2 0 series static electricity because semiconductor device s are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electrici ty. (2) electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) eliminate static body electricity by the use of rings or bracelets connecte d to ground through high resis tance (on the level of 1 m ). wearing of condu ctive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti - static measures. (5) avoid the use of styrofoam or other highly static - prone mat erials for st orage of completed board assem blies.
document number: 002 - 04863 rev.*d page 35 of 141 s6j31 2 0 series 5.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. (2) discharge of static electricity when high - voltage charges exist close to semic onductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving ex posure to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 04863 rev.*d page 36 of 141 s6j31 2 0 series 6. h andling d evices for l atch - up p revention the latch - up phenomenon may occur on a cmos ic in the following cases: the voltage applied to an input or output pin is higher than v cc or lower than v ss ; or the voltage applied between a vcc pin and a vss pin exceeds the rating. a latch - up causes a rapid increase in the power supply current , possibly resulting in thermal damage to an element. when using the device, take sufficient care not to exceed the maximum rating. also be careful that analog power supplies (avcc0, avcc1, avrh0, and avrh1) and analog inputs do not exceed the digital pow er supply (vcc) at the analog system power - on and power - off times. vcc and dvcc must be set to the same voltage. the power - on sequence is as follows. simultaneously turn on the digital supply voltage (vcc) and analog supply voltages (avcc0, avcc1, avrh0, a nd avrh1), and the power supply voltage of high - current output buffer pins (dvcc), or turn on the digital supply voltage (vcc) and then the analog supply voltages (avcc0, avcc1, avrh0, and avrh1) , and the power supply voltage of high - current output buffer pins (dvcc) . about h andling u nused p ins leaving unused input pins open may cause permanent damage from a malfunction or latch - up. take measures for unused pins, such as pulling up or pulling down the voltage with resistors of 2 kiloohms or higher. if there are any unused input/output pins, set them to the output state and then open them, or set them to the input state and h andle them in the same way as input pins. about p ower s upply p ins if the device has multiple vcc and vss pins, the device is design ed in such a way that the pins that should be at the same potential are connected to each other inside the device to prevent malfunctions such as latch - up. however, to reduce unwanted emissions, prevent malfunctions of strobe signals caused by an increase of the ground level, and observe standards on total output current, be sure to connect all the vcc and vss pins to the power source and ground externally. also handle all the vss power supply pins in this way as shown in the following diagram. if there are multiple vcc or vss systems, the device does not operate normally even within the guaranteed operating range.
document number: 002 - 04863 rev.*d page 37 of 141 s6j31 2 0 series figure 8 - 1 pin assignment in addition, consider connecting with low impedance from the power supply source to the vcc and vss of this device. in the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of c pin is recommende d to use as a bypass capacitor between the vcc pin and the vss pin. about the c rystal o scillation c ircuit noise entering the x0 or x1 pin may cause a malfunction. design the printed circuit board in such a way that the x0 and x1 pi ns, the crystal oscillator (or ceramic resonator), and a bypass capacitor to ground are located very close to the device. we recommend that the printed circuit board artwork have the x0 and x1 pins enclosed by ground. about the mode pin (md) use mode pin md by directly connecting it to a vcc o r vss pin. to prevent noise from causing the device to accidentally enter test mode, reduce the pattern length between each mode pin and a vcc or vss pin on the printed circuit board, and connect them wit h low impedance. about the power - on time to prevent a malfunction of the voltage step - down circuit built in the device, the voltage rising must be monotonic during power - on point to note during pll clock operation while a pll clock is selected, if the oscillator breaks off or input stops, the pll clock may continue operating with the free running frequency of the internal self - oscillator circuit. this operation is outside of the guaranteed range. power supply pin processing of an a/d converter even when no a/d converter is used, establish a connection such t hat av cc =avrh= v cc and av ss av ss /avrl= v ss . points to note about using external clocks external clocks are not supported. external direct clock input cannot be used.
document number: 002 - 04863 rev.*d page 38 of 141 s6j31 2 0 series power - on sequence of the power supply analog inputs of an a/d converter be sure to turn on the digital power supply (vcc) before the application of the power supplies ( av cc , avrh, and avrl) and analog inputs ( an3, an5 to an6, an9 to an10, an12 to an15, an17 to an24, an27 to an43, an46 to an53, and an55 to an62 ) of an a/d converter. at the po wer - off time, turn off the power supplies and analog inputs of the a/d converter, and then turn off the digital power supply (vcc). perform these power - on and power - off operations without avrh exceeding avcc. even when using a pin shared with an analog inp ut as an input port, do not allow the input voltage to exceed avcc. (turning on or off the analog supply voltage and digital supply voltage simultaneously is not a problem.) treatment of power supplies for high current output buffer pins (dvcc, dvss) be su re to turn on the digital power supply voltage (vcc) first, and then turn on the power supply voltage for high current output buffer pins (dvcc, dvss). also, turn off the power supplies for high current output buffer pins first, and then turn off the digit al power supply voltage (vcc). even if the high current output buffer pins are used as general - purpose ports, the power supply voltage of high current output buffer pins (dvcc, dvss) must be powered. (the power supplies of high current output buffer pins a nd the digital power supplies can be turned on or off simultaneously.) connect the pins to have dvcc=vcc and dvss=vss. about c pin processing this d evice has a built - in voltage step - down circuit. be sure to connect a capacitor to the c pin (pin 1 26 in s6j3 1 2 x h zc * specifications ) for internal stabilization of the device. for the standard values, see "recommended operating conditions" in the latest data sheet. x:a/9/8, z: a/b precautions on designing a mounting substrate measures against heat generation from the package must be taken for the mounting substrate to observe the absolute maximum rating (operating temperature). design a mounting substrate with 4 or more layers. connect the back of the package stage and the substrate pad with solder paste. arra nge thermal via holes on the substrate pad. for detailed information about mount conditions, contact your sales representative. notes on writing to a register containing a status flag in writing to a register containing a status flag (particularly an inter rupt request flag, etc.) to control a function, it is important to take care not to accidentally clear the status flag. therefore, before the write operation, configure the status bit such that the flag is not cleared, and then set the control b it to the desired value. especially for control bits configured as a set of multiple bits, bit instructions cannot be used (bit instructions have only 1 - bit access). in such cases, byte, half - word, or word access is used to write to the control bits and a status fl ag simultaneously. however, at this time, be careful not to accidentally clear bits other than the intended ones (the status flag bit in this case). note: bit instructions take this point into account for registers that support bit - band units, so it does n ot need to be a concern. you need to take care when using bit instructions for registers that do not support bit - band units.
document number: 002 - 04863 rev.*d page 39 of 141 s6j31 2 0 series 7. b lock d iagram this section provides block diagrams of the s6j31 2 0 series. figure 9 - 1 s6j312 x h z c * block diagram * x: a/9/8, z: a/b c p p common peri #1 group common peri #2 group common peri #0 group system controller(sysc) sysc1 memory & config group core group ( 1 - core) debug group (coresighttm) dap tc ram #0 (2bank) 64kb (32kb 2)/ 48kb (24kb 2)/ 32kb (16kb 2) bootrom 16kb timing protection (tpu) #0 debug i/f (jtag/swd) ahb - m apb - s apb - m procceser b0tcm atcm #0 b1tcm #0 llpp ax i32 - m ahb32 axi - m axi - s c pu #0 irc #0 512 vectors ram security ahb - 64 apb - 32 jtag wakeup i$ #0 16kb d$ #0 16kb mpu #0 dmac complex #0 - dmac 16.ch - reloadtimer 4ch jtag_swclktck clk_dbg trace group system sram 16kb wakeup request #0 etm tm # 0 debug apb debug apb atb ahb 2apb (priviledge protection) trace i/ f(8pin) etb (trace buffer) 16kb a h b - 64 security checker cortex tm - r5 clk_ atb flash group i/f low latency peripheral bus matrix (llpbm) she group bus config group - bus performance counters - misc register module from/to commonperi#2 a h b - 32 from/to commonperi#2 dmac config a xi - 64 a h b - 32 axi - 64 axi - 64 a h b - 32 a h b - 32 a h b - 32 from/to flash group from/to memory config grp. clock divide and distribution power domain 2 mcu config group ecc - ed ram i/f backup ram 4kb (8+5 bit width ram x 4) backup ram 4kb (8+5 bit width ram x 4) eicu 16ch power domain 6_0 power domain 4_ 0 ahb - 32 clk_sysch0h a hb - 32 state manage (2) clk_dma ahb - 32 power domain 1 (always on) eam a xi - 64 clk_ sysc1 sw - watchdog csv(for pll) high performance matrix (hpm) can - fd 3 ch ahb - 32 ppu master from/to commonperi#2 from/to ppu - slaves clk_hpm2 clk_hpm clk_hpm clk_llpbm2 clk_she flash group tcflash #0 1mb/768kb/512kb + 64kb + work flash #0 112 kb workflash tcf tcf tcf ahb - 64 ahb - 64 axi - 64 atcm #0 (reg & data) (reg) (data) from/to memory config grp. axi - 64 clk_cpu clk_fclk clk_cpu clk_memc clk_hpm clk_hpm clk_hpm clk_memc clk_hpm clk_memc clk_hpm clk_llpbm2 clk_llpbm clk_lcp0a clk_lcp0a clk_hpm clk_hpm clk_hpm2 clk_cpu axi - 64 clk_cpu clk_cpu clk_cpu clk_memc clk_ sysc1 clk_lcp canfd_cclk clk_ram0h clk_ram1h clk_trc clk_cpu clk_dbg clk_she clk_she bbu bbu bbu bbu bbu clk_llpbm2 a hb - 32 clk_llpbm clk_llpbm clk_llpbm clk_llpbm ram base timer 30ch m.f.s 5ch 32bit frt 6ch 32bit icu 12ch 32bit ocu 12ch 12bit a/dc unit0 22ch peripheral bus bridge peripheral bus bridge peripheral bus bridge crc 4ch gpio dmac complex #0 (config) ppu master (cnofig) bus config group (config) h/w watchdog reset manage clock manage csv ponr state manage source clock timer lvd fast - cr slow - cr pll0 sscg pll0 wakeup - detect rtc power manage ext - irq 16ch nmi clock calibration clk_cpu a hb - 64 a hb - 64 clk_memc power domain 4_1 a h b - 32 axi - 32 #0 tcm sram (config) from/to core - group clk_memc power domain 3 power domain 3 reload timer 4ch sg 3ch a h b - 32 clk_llpbm clk_lcp1a clk_lcp1a bbu peripheral bus bridge reload timer 4ch reload timer 2ch qprc 2ch smc 4ch ddrhsspi group axi2ahb axi - 32 clk_hsspi ddr hsspi lcdc 32seg 4com common peri #0 group power domain 1 (always on) partial wake up 12bit a/dc unit1 28ch m.f.s 5ch ebi group axi2ahb axi - 32 clk_extbus ebi can prescaler (clk_can) clk_comh
document number: 002 - 04863 rev.*d page 40 of 141 s6j31 2 0 series 8. m emory m ap this section explains the memory map. figure 10 - 1 memory map (s6j31 2ahz c /9hz c /8hz c *) * z : a/b s6j312ahzc* s6j3129hzc* s6j3128hzc* start end group part part part 0x0000_0000 0x0000_7fff tcram (main 32kbyte) 0x0000_8000 0x0000_bfff reserved 0x0000_c000 0x0000_ffff reserved reserved 0x0001_0000 0x007f_ffff reserved reserved reserved 0x0080_0000 0x008f_ffff reserved reserved reserved 0x009f_0000 0x009f_ffff tcm_flash (small sector 8kbyte8) tcm_flash (small sector 8kbyte8) tcm_flash (small sector 8kbyte8) 0x00a0_0000 0x00a7_ffff tcm_flash (code 512kbyte) 0x00a8_0000 0x00ab_ffff reserved 0x00ac_0000 0x00af_ffff reserved reserved 0x00b0_0000 0x00df_ffff reserved reserved reserved 0x00e0_0000 0x00ff_ffff reserved reserved reserved 0x0100_0000 0x019e_ffff reserved reserved reserved 0x019f_0000 0x019f_ffff axi_flash_memory (small sector 8kbyte8 *mirror) axi_flash_memory (small sector 8kbyte8 *mirror) axi_flash_memory (small sector 8kbyte8 *mirror) 0x01a0_0000 0x01a7_ffff axi_flash_memory (code 512kbyte *mirror) 0x01a8_0000 0x01ab_ffff reserved 0x01ac_0000 0x01af_ffff reserved reserved 0x01b0_0000 0x01df_ffff reserved reserved reserved 0x01e0_0000 0x01ff_ffff reserved reserved reserved 0x0200_0000 0x0200_3fff system sram (16kbyte) system sram (16kbyte) system sram (16kbyte) 0x0200_4000 0x0203_ffff reserved reserved reserved 0x0204_0000 0x027f_ffff reserved reserved reserved 0x0280_0000 0x0280_002f exclusive access memory exclusive access memory exclusive access memory 0x0280_0030 0x03ff_ffff reserved reserved reserved 0x0400_0000 0x05ff_ffff axi_slave_core0 axi_slave_core0 axi_slave_core0 0x0e01_c000 0x0e0f_ffff reserved reserved reserved 0x0e10_0000 0x0e1f_ffff reserved reserved reserved 0x0e21_c000 0x0e2f_ffff reserved reserved reserved 0x0e31_c000 0x0e3f_ffff reserved reserved reserved 0x0e40_0000 0x0e7f_ffff reserved reserved reserved 0x0e80_0000 0x0e80_1fff backup ram 8kbyte backup ram 8kbyte backup ram 8kbyte 0x0e80_2000 0x0e80_ffff reserved reserved reserved 0x0e81_0000 0x0e87_ffff reserved reserved reserved 0x1000_0000 0x1fff_ffff external bus area ebi_memory(sram/flash) ebi_memory(sram/flash) ebi_memory(sram/flash) 0x8000_0000 0x8fff_ffff hsspi memory area hsspi0_memory hsspi0_memory hsspi0_memory 0xb000_0000 0xb483_ffff peri_area peri_area peri_area 0xb484_0000 0xb484_ffff apps#5 apps#5 apps#5 0xb48c_0000 0xb48c_ffff apps#7 apps#7 apps#7 0xb48d_0000 0xb7ff_ffff peri_area peri_area peri_area 0xb800_0000 0xbfff_ffff 0xfffe_e000 0xfffe_ffff error config errcfg errcfg errcfg 0xffff_0000 0xffff_3fff bootrom bootrom bootrom 0xffff_4000 0xffff_ffff reserved reserved reserved 0xc000_0000 0xfffe_dfff reserved bootrom peri_area peri_area peri_area reserved reserved reserved peri area 0xb485_0000 0xb48b_ffff 0x9000_0000 0xafff_ffff reserved reserved reserved reserved 0x2000_0000 0x7fff_ffff reserved reserved reserved reserved reserved reserved reserved 0x0e88_0000 0x0fff_ffff 0x0e30_0000 0x0e31_bfff work_flash (112kbyte mirror area 4) work_flash (112kbyte mirror area 4) work_flash (112kbyte mirror area 4) 0x0e20_0000 0x0e21_bfff work_flash (112kbyte mirror area 3) work_flash (112kbyte mirror area 3) work_flash (112kbyte mirror area 3) reserved 0x0e00_0000 0x0e01_bfff work_flash (112kbyte mirror area 1) work_flash (112kbyte mirror area 1) work_flash (112kbyte mirror area 1) 0x0600_0000 0x0dff_ffff reserved reserved axi_flash_memory (code 1mbyte *mirror) axi_flash_memory (code 768kbyte *mirror) shared flash and memory area tcram (main 64kbyte) tcram (main 48kbyte) tcm_flash (code 1mbyte) tcm_flash (code 768kbyte) adress internal area for cr5 complex
document number: 002 - 04863 rev.*d page 41 of 141 s6j31 2 0 series ? only the cpu core can access 0000_0000 ~ 01ff_ffff. bus masters other than the cpu core cannot access the region. ? internal area of cr5 complex (0000_0000 ~ 01ff_ffff) is mapped to axi_slave_core0. all bus masters can access to internal area of cr5 complex via axi_slave_core0. ? in each of the following memory area combinations, the areas are physically the same memory area. 1. tcm flash (0x00a0_0000 - ) and axi flash memory (0x01a0_0000 - ) 2. tcm flash small sector (0x0 0 9f_0000 - ) and axi flash memory small sector (0x019f_0000 - ) 3. workflash (0x0e00_0000 - ), workflash (0x0e20_0000 - ), and workflash (0x0e30_0000 - ) the ecc moveme nt in tcm port is based on ecc setting inside the cpu. ? the differences between the tcm flash and axi flash include the following. function tcm flash axi flash high - speed access using dedicated bus applicable not applicable write and erase not applicable (read - only) applicable read applicable applicable ? the differences between workflash areas include the following. area function workflash area 1 used in write operation (with ecc) workflash area 3 used in write operation (without ecc) workflash area 4 used in read operation ? terms are as follows. term description tcm ram main ram tcm flash program flash (tcm area) axi flash program flash (axi area) this is physically the same as the tcm flash. system ram system ram axi slave core axi cpu control area workflash flash for work backup ram backup ram ebi memory memory for external bus interface hsspi0 memory memory for ddr hs - spi peri area entire area for peripheral functions apps#5 part of area for peripheral functions apps#7 part of area for peripheral functions errcfg error configuration area bootrom rom for reset boot
document number: 002 - 04863 rev.*d page 42 of 141 s6j31 2 0 series s6j31 2 x h zc * peripheral map * x: a/9/8 , z:a/b start address end address group function ppu no b000_0000 b010_7fff reserved - b010_0000 b010_03ff ebi registers 0 b010_0400 b010_0fff reserved - b010_1000 b010_13ff ddr_hsspi 1 b010_0400 b010_7fff reserved - b010_8000 b010_80ff systemsram systemsram registers - b010_8100 b02f_ffff reserved - b030_0000 b030_7fff sysc1 system controller #1 - b030_8000 b03f_ffff sysc1 swdt - b040_0000 b040_7fff m em ory_config_group irc0 21 b040_8000 b040_ffff m em ory_config_group tpu0 19 b041_0000 b041_0fff m em ory_config_group tcram control status register 16 b041_1000 b041_1fff m em ory_config_group tcflash control status register 17 b041_2000 b041_20ff m em ory_config_group wflash control status register 18 b041_2100 b04f_ffff reserved - b050_0000 b05f_ffff reserved - b060_0000 b060_007f m cu_config_group protection register area - b060_0080 b060_00ff m cu_config_group run profile register area - b060_0100 b060_017f m cu_config_group pss profile register area - b060_0180 b060_01ff m cu_config_group app profile register area - b060_0200 b060_027f m cu_config_group sts profile register area - b060_0280 b060_02ff m cu_config_group system register area - b060_0300 b060_037f m cu_config_group csv - b060_0380 b060_03ff m cu_config_group reset - b060_0400 b060_047f m cu_config_group sct(fast cr) 34 b060_0480 b060_04ff m cu_config_group sct(slow cr) 33 b060_0500 b060_05ff m cu_config_group sct(m ain clock) 35 b060_0600 b060_067f m cu_config_group clock system - b060_0680 b060_06ff m cu_config_group special register area - b060_0700 b060_07ff m cu_config_group debug register area - b060_0800 b060_bfff m cu_config_group m ode - b060_c000 b060_ffff m cu_config_group hwdt - b061_0000 b061_7fff reserved - b061_8000 b061_ffff m cu_config_group rtc 32 b062_0000 b063_ffff m cu_config_group eic - b064_0000 b065_ffff reserved - b066_0000 b067_ffff reserved - b068_0000 b068_7fff m cu_config_group buram if - b068_8000 b068_83ff m cu_config_group eicu 37 b068_8400 b068_87ff m cu_config_group cr_calibration 38 b068_8800 b068_8bff m cu_config_group irq all 42 b068_8c00 b068_ffff m cu_config_group can prescaler 43 b069_0000 b06f_ffff reserved - b070_0000 b07f_ffff reserved - b080_0000 b0ff_ffff bit rm w alias bbu for m cu config (covers b060_0000 -- b06f_ffff) - b100_0000 b10f_ffff bit rm w alias bbu for sysc1 (covers b030_0000 -- b031_ffff) - b110_0000 b11f_ffff bit rm w alias bbu for m em c (covers b040_0000 -- b041_ffff) - b120_0000 b1ff_ffff reserved - b200_0000 b20f_ffff she she configuration registers 63 b210_0000 b46f_ffff reserved -
document number: 002 - 04863 rev.*d page 43 of 141 s6j31 2 0 series start address end address group function ppu no b470_0000 b470_3fff commonperi #2 dm ac #0 registers 64 b470_4000 b470_ffff reserved - b471_0000 b471_0fff commonperi #2 m pu for dm ac#0 66 b471_1000 b471_3fff reserved - b471_4000 b471_4fff commonperi #2 dm a complex #0 registers (additional registers, rlts) 68 b471_5000 b471_7fff reserved - b471_8000 b471_83ff commonperi #2 crc#0 70 b471_8400 b471_87ff commonperi #2 crc#1 71 b471_8800 b471_8bff commonperi #2 crc#2 72 b471_8c00 b471_8fff commonperi #2 crc#3 73 b471_9000 b473_7fff reserved - b473_8000 b473_ffff commonperi #2 gpio 74 b474_0000 b474_7fff commonperi #2 ppc 75 b474_8000 b474_ffff commonperi #2 ric 76 b475_0000 b475_7fff commonperi #2 ppu - b475_8000 b478_7fff reserved - b478_8000 b478_83ff commonperi #2 reload timer ch.32 160 b478_8400 b478_87ff commonperi #2 reload timer ch.33 161 b478_8800 b478_fbff reserved - b478_fc00 b478_ffff commonperi #2 m isc registers 82 b479_0000 b47f_ffff reserved - b480_0000 b480_03ff commonperi #0 m .f.serial ch.0 176 b480_0400 b480_07ff commonperi #0 m .f.serial ch.1 177 b480_0800 b480_0bff commonperi #0 m .f.serial ch.2 178 b480_0c00 b480_0fff commonperi #0 m .f.serial ch.3 179 b480_1000 b480_13ff commonperi #0 m .f.serial ch.4 180 b480_1400 b480_7fff reserved - b480_8000 b480_83ff commonperi #0 basetimer ch.0 88 b480_8400 b480_87ff commonperi #0 basetimer ch.1 89 b480_8800 b480_8bff commonperi #0 basetimer ch.2 90 b480_8c00 b480_8fff commonperi #0 basetimer ch.3 91 b480_9000 b480_93ff commonperi #0 basetimer ch.4 92 b480_9400 b480_97ff commonperi #0 basetimer ch.5 93 b480_9800 b480_9bff commonperi #0 basetimer ch.6 94 b480_9c00 b480_9fff commonperi #0 basetimer ch.7 95 b480_a000 b480_a3ff commonperi #0 basetimer ch.8 96 b480_a400 b480_a7ff commonperi #0 basetimer ch.9 97 b480_a800 b480_abff commonperi #0 basetimer ch.10 98 b480_ac00 b480_afff commonperi #0 basetimer ch.11 99 b480_b000 b480_ffff reserved - b481_0000 b481_03ff commonperi #0 reload timer ch.0 128 b481_0400 b481_07ff commonperi #0 reload timer ch.1 129 b481_0800 b481_0bff commonperi #0 reload timer ch.2 130 b481_0c00 b481_0fff commonperi #0 reload timer ch.3 131 b481_1000 b481_ffff reserved - b482_0000 b482_03ff commonperi #0 frt ch.0 208 b482_0400 b482_07ff commonperi #0 frt ch.1 209 b482_0800 b482_0bff commonperi #0 frt ch.2 210 b482_0c00 b482_0fff commonperi #0 frt ch.3 211 b482_1000 b482_13ff commonperi #0 frt ch.4 212 b482_1400 b482_17ff commonperi #0 frt ch.5 213 b482_1800 b482_7fff reserved - b482_8000 b482_83ff commonperi #0 icu ch.0 / ch.1 224 b482_8400 b482_87ff commonperi #0 icu ch.2 / ch.3 225 b482_8800 b482_8bff commonperi #0 icu ch.4 / ch.5 226 b482_8c00 b482_8fff commonperi #0 icu ch.6 / ch.7 227 b482_9000 b482_93ff commonperi #0 icu ch.8 / ch.9 228 b482_9400 b482_97ff commonperi #0 icu ch.10 / ch.11 229 b482_9800 b482_ffff reserved -
document number: 002 - 04863 rev.*d page 44 of 141 s6j31 2 0 series start address end address group function ppu no b483_0000 b483_03ff commonperi #0 ocu ch.0 / ch.1 240 b483_0400 b483_07ff commonperi #0 ocu ch.2 / ch.3 241 b483_0800 b483_0bff commonperi #0 ocu ch.4 / ch.5 242 b483_0c00 b483_0fff commonperi #0 ocu ch.6 / ch.7 243 b483_1000 b483_13ff commonperi #0 ocu ch.8 / ch.9 244 b483_1400 b483_17ff commonperi #0 ocu ch.10 / ch.11 245 b483_1800 b483_fbff reserved - b483_fc00 b483_ffff common peri #0 m isc registers 80 b484_0000 b484_ffff apps #5 apps#5 area - b485_0000 b487_ffff reserved - b488_0000 b488_03ff commonperi #1 m .f.serial ch.8 184 b488_0400 b488_07ff commonperi #1 m .f.serial ch.9 185 b488_0800 b488_0bff commonperi #1 m .f.serial ch.10 186 b488_0c00 b488_0fff commonperi #1 m .f.serial ch.11 187 b488_1000 b488_13ff commonperi #1 m .f.serial ch.12 188 b488_1400 b488_ffff reserved - b489_0000 b489_03ff commonperi #1 reload timer ch.16 144 b489_0400 b489_07ff commonperi #1 reload timer ch.17 145 b489_0800 b489_0bff commonperi #1 reload timer ch.18 146 b489_0c00 b489_0fff commonperi #1 reload timer ch.19 147 b489_1000 b489_7fff reserved - b489_8000 b489_83ff commonperi #1 qprc ch.8 200 b489_8400 b489_87ff commonperi #1 qprc ch.9 201 b489_8800 b48b_0fff reserved - b48b_1000 b48b_fbff reserved - b48b_fc00 b48b_ffff commonperi #1 m isc registers 81 b48c_0000 b48c_ffff apps #7 apps#7 area - b48d_0000 b48f_ffff reserved - b490_0000 b490_ffff commonperi #0 can_fd ch.0 256 b491_0000 b491_ffff commonperi #0 can_fd ch.1 257 b492_0000 b492_ffff commonperi #0 can_fd ch.2 258 b493_0000 b4bf_ffff reserved - b4c0_0000 b4ff_ffff bit rm w alias bbu for commonperi#0 (covers b490_0000 -- b497_ffff) - b500_0000 b5ff_ffff reserved - b600_0000 b6ff_ffff reserved - b700_0000 b77f_ffff bit rm w alias bbu alias for commonperi#2 (covers b470_0000 -- b47f_ffff) - b780_0000 b7bf_ffff bit rm w alias bbu alias for commonperi#0 (covers b480_0000 -- b487_ffff) - b7c0_0000 b7ff_ffff bit rm w alias bbu alias for commonperi#1 (covers b488_0000 -- b48f_ffff) - b800_0000 fffe_dfff reserved - fffe_e000 fffe_fbfc error config irc - fffe_fc00 fffe_ffff error config bootrom i/f 20
document number: 002 - 04863 rev.*d page 45 of 141 s6j31 2 0 series ? - apps#5 area ? - apps#7 area when mpu attribute of cortex ? - r5 is configured as "normal", store buffer inside cortex ? - r5 can operate and write data can be merged. to avoid influence of this data merger, mpu attribute "device" or "strongly ordered" should be used. mpu attribute "device" or "strongly ordered" must b e used for areas below, to avoid this influence. ? backup ram area (backup_ram) [0e80_0000 ~ 0e87_ffff] ? peripheral area (peri area) [b000_0000 ~ b7ff_ffff] ? error config area (errcfg) [fffe_e000 ~ fffe_ffff] mpu attribute "device" or "strongly ordered" is req uired for accesses to areas below, in particular situation. ? flash memory (when writing commands) she off product is prohibited to access she area (b200_0000 to b20f_ffff) start address end address function ppu no b484_0000 b484_03ff apps #5 sound generator ch.0 264 b484_0400 b484_07ff apps #5 sound generator ch.1 265 b484_0800 b484_0bff apps #5 sound generator ch.2 266 b484_0c00 b484_37ff reserved - b484_3800 b484_3bff apps #5 basetimer ch.12 278 b484_3c00 b484_3fff apps #5 basetimer ch.13 279 b484_4000 b484_43ff apps #5 basetimer ch.14 280 b484_4400 b484_47ff apps #5 basetimer ch.15 281 b484_4800 b484_4bff apps #5 basetimer ch.16 282 b484_4c00 b484_4fff apps #5 basetimer ch.17 283 b484_5000 b484_53ff apps #5 basetimer ch.18 284 b484_5400 b484_57ff apps #5 basetimer ch.19 285 b484_5800 b484_5bff apps #5 basetimer ch.20 286 b484_5c00 b484_5fff apps #5 basetimer ch.21 287 b484_6000 b484_63ff apps #5 basetimer ch.22 288 b484_6400 b484_67ff apps #5 basetimer ch.23 289 b484_6800 b484_6bff apps #5 basetimer ch.24 290 b484_6c00 b484_6fff apps #5 basetimer ch.25 291 b484_7000 b484_73ff apps #5 basetimer ch.26 292 b484_7400 b484_77ff apps #5 basetimer ch.27 293 b484_7800 b484_7bff apps #5 basetimer ch.28 294 b484_7c00 b484_7fff apps #5 basetimer ch.29 295 b484_8000 b484_83ff apps #5 a/d unit0 296 b484_8400 b484_87ff apps #5 a/d unit1 , partial wake up 297 b484_8800 b484_8bff apps #5 a/d analog input control 298 b484_8c00 b484_8fff reserved - b484_9000 b484_93ff apps #5 global timer 300 b484_9400 b484_ffff reserved - start address end address function ppu no b48c_0000 b48c_3fff reserved - b48c_4000 b48c_43ff apps #7 stepper m otor control ch.0 317 b48c_4400 b48c_47ff apps #7 stepper m otor control ch.1 318 b48c_4800 b48c_4bff apps #7 stepper m otor control ch.2 319 b48c_4c00 b48c_4fff apps #7 stepper m otor control ch.3 320 b48c_5000 b48c_57ff reserved - b48c_5800 b48c_5bff apps #7 sm c trigger generator 323 b48c_5c00 b48c_5fff apps #7 liquid crystal display controller 324 b48c_6000 b48c_63ff apps #7 liquid crystal display input/output control 325 b48c_6400 b48c_ffff reserved -
document number: 002 - 04863 rev.*d page 46 of 141 s6j31 2 0 series 9. p in s tatuses i n cpu s tatus table 11 - 1 pin state table (1/2) external factor generation in progress internal reset issuance in progress internal reset issuance in progress after internal reset issuance (before gport setting) before internal reset issuance internal reset issuance in progress internal reset issuance in progress after internal reset issuance (before gport setting) internal reset issuance in progress after internal reset issuance (before gport setting) cpu sleep mode high impedance disabled (sysc0_specfgr. psspadctrl=0) when high impedance enabled (sysc0_specfgr. psspadctrl=1) high impedance disabled (sysc0_specfgr. psspadctrl=0) when high impedance enabled (sysc0_specfgr. psspadctrl=1) 2 p000/sot2_1/ain8_0/mad00/seg8 3 p001/scs20_1/bin8_0/mdata15/seg9 4 p003/scs22_1/zin8_0/mdata14/seg10 5 p005/sin3_0/in6_0/ain9_0/mdata13/seg11 6 p006/sot3_0/sda3_0/in7_0/bin9_0/mdata12/seg12 7 p007/sck3_0/scl3_0/in8_0/zin9_0/mdata11/seg13 8 p008/scs30_0/in9_0/tioa0_0/mdata10/seg14 9 p009/int0_1/sin11_0/in10_0/tioa1_0/mdata09/seg15 hi-z/input blocked *1 hi-z/input blocked *1 10 p010/sot11_0/sda11_0/in11_0/tioa2_0/mdata08/seg16 11 p012/sck11_0/scl11_0/out5_0/tioa3_0/moex/seg17 12 p013/scs110_0/out6_0/tioa4_0/mwex/seg18 13 p015/scs111_0/out7_0/tioa5_0/mcsx0/seg19 14 p016/scs112_0/out8_0/tioa6_0/mcsx1/seg20 15 p017/scs113_0/out9_0/tioa7_0/mdqm0/seg21 16 p018/out10_0/tioa8_0/mdqm1/seg22 17 p019/text0_0/out11_0/tiob0_0/mad15/seg23/st0 *9 output "l"/ last status retained output "l"/ input blocked 18 p020/sot0_0/sda0_0/text1_0/tiob1_0 19 p 021/sck0_0/scl0_0/sck4_1/tiob2_0 20 p022/int3_0/sin0_0/tiob3_0 hi-z/input blocked *1 hi-z/input blocked *1 21 p023/scs0_0/sin4_1/tiob4_0/mad16/seg24/st1 *9 22 p024/sot4_1/tiob5_0/mad17/seg25/st2 *9 23 p027/scs42_1/text0_1/tiob6_0/tioa4_1/mad18/seg26/st3 *9 24 p028/sin1_0/out0_1/tiob7_0/mad19/seg27/st4 *9 25 p029/sot1_0/out1_1/mad20/seg28/st5 *9 26 p030/scs43_1/out2_1/tiob8_0/mad21/seg29/st6 *9 27 p031/scs1_0/out3_1/mad22/seg30/st7 *9 28 p100/sck1_0/out4_1/mad23/seg31/st8 *9 29 p101/an3/out5_1/mdata07 30 p103/an5/out6_1/tiob9_0/mdata06 31 p105/out7_1/tioa9_0/mdata05 32 p106/tx1_2/out8_1/tin0/mdata04 33 p107/int2_1/rx1_2/out9_1/tioa10_0/tot0/mdata03 34 p108/int3_1/an6/out10_1/tioa11_0/tin1/mrdy 35 p109/out11_1/tioa12_0/tot1/mclk 39 p112/an9/tioa13_0/tin2/mdata02 40 p113/tioa5_1/tot2/mdata01 41 p114/an10/tioa6_1/tin3/mdata00 45 p115/tiob10_0/tot3 46 p117/int4_1/an12/tiob11_0/tin16 47 p118/int5_1/an13/tiob12_0/tot16 48 p119/an14/scs90_0/tiob13_0/tin17 49 p120/an15/scs91_0/tot17 50 p122/an17/scs92_0/tioa11_1/sga0_0 51 p123/an18/scs93_0/tioa12_1/sgo0_0 52 p126/an19/sga1_0 53 p127/an20/text1_1/sgo1_0 54 p128/an21/text2_1/sga2_0 55 p129/an22/in6_1/sgo2_0 56 p130/int5_0/an23/sin9_0/in7_1 hi-z/input blocked *1 hi-z/input blocked *1 57 p131/an24/sot9_0/sda9_0/in8_1 hi-z/input blocked hi-z/input blocked 58 p202/int6_1/sck9_0/scl9_0/in9_1 hi-z/input blocked *1 hi-z/input blocked *1 59 p203/in10_1/tiob19_0/ain8_1 60 p204/an27/in11_1/tiob20_0/bin8_1 61 p205/an28/text3_1/tiob21_0/zin8_1 62 p206/an29/scs43_0/text4_1/tiob22_0 63 p207/int7_1/an30/sck4_0/scl4_0/text5_1/spisel3 hi-z/input blocked *1 hi-z/input blocked *1 64 p208/an31/scs42_0/tioa19_0/spisel2 65 p209/an32/sot4_0/sda4_0/tioa20_0/spisel1 66 p210/int6_0/an33/sin4_0/in0_2/tioa21_0/spiclk hi-z/input blocked *1 hi-z/input blocked *1 67 p211/an34/scs40_0/in1_2/tioa22_0/spidat0 68 p212/an35/scs41_0/scs80_1/in2_2/tioa13_1/spidat2 69 p213/int8_1/sin8_1/in3_2/tioa14_1/spidat1 hi-z/input blocked *1 hi-z/input blocked *1 70 p214/sot8_1/in4_2/tioa15_1/spisel0 hi-z/input blocked hi-z/input blocked 71 p215/int9_1/sck8_1/in5_2/tioa16_1/spidat3 hi-z/input blocked *1 hi-z/input blocked *1 external reset factor 3 internal reset factor *2 sleep mode stop mode *4 timer mode *4 after external factor releasing external factor generation in progress after external factor releasing pin no. pin name gporten control external reset factor 1 external reset factor 2 status immediately before the shutdown retaine *6 last state retained last state retained *3 *6 hi-z/input blocked *6 last state retained *3 *6 hi-z/input blocked *6 hi-z/input blocked *6 hi-z/input blocked *6 hi-z/input blocked last state retained *3 hi-z/input blocked output "l"/input blocked output "l"/ last status retained output "l"/ input blocked output "l"/ input blocked output "l"/ input blocked status immediately before the shutdown retaine *6 last state retained *3 *6 hi-z/input blocked *6 last state retained *3 *6 hi-z/ last status retained hi-z/ input blocked hi-z/ input blocked hi-z/ input blocked status immediately before the shutdown retaine last state retained *3 hi-z/input blocked hi-z/input blocked *1 hi-z/input blocked *1 hi-z/input blocked hi-z/input blocked hi-z/input blocked *6 hi-z/input blocked hi-z/ last status retained hi-z/ input blocked hi-z/ input blocked hi-z/ input blocked status immediately before the shutdown retaine last state retained *3 hi-z/input blocked last state retained *3 with control hi-z/input blocked hi-z/ last status retained hi-z/ input blocked hi-z/input blocked hi-z/input blocked output "l"/input blocked output "l"/ input blocked output "l"/ input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked *1 hi-z/input blocked *1 hi-z/input blocked hi-z/input blocked
document number: 002 - 04863 rev.*d page 47 of 141 s6j31 2 0 series table 11 - 2 pin state table (2/2) external factor generation in progress internal reset issuance in progress internal reset issuance in progress after internal reset issuance (before gport setting) before internal reset issuance internal reset issuance in progress internal reset issuance in progress after internal reset issuance (before gport setting) internal reset issuance in progress after internal reset issuance (before gport setting) cpu sleep mode high impedance disabled (sysc0_specfgr. psspadctrl=0) when high impedance enabled (sysc0_specfgr. psspadctrl=1) high impedance disabled (sysc0_specfgr. psspadctrl=0) when high impedance enabled (sysc0_specfgr. psspadctrl=1) 74 p218/an36/text2_0/tiob14_0 75 p219/an37/text3_0/tiob15_0 76 p220/an38/tx2_0/scs83_0/in6_2/tiob16_0 77 p222/int7_0/an39/rx2_0/sin8_0/in7_2 hi-z/input blocked *1 hi-z/input blocked *1 78 p223/an40/pwu_an0/scs81_0/in8_2/ain9_1 79 p224/an41/pwu_an1/tx0_2/scs80_0/in9_2/bin9_1 80 p225/int0_0/an42/pwu_an2/rx0_2/sot8_0/sda8_0/in10_2/tiob17_0/zin9_1 hi-z/input blocked *1 hi-z/input blocked *1 81 p226/an43/pwu_an3/sck8_0/scl8_0/in11_2/tioa17_1 hi-z/input blocked hi-z/input blocked 87 p229/int8_0/an46/pwu_an6/out0_0/tioa25_0/pwm1p0 hi-z/input blocked *1 hi-z/input blocked *1 88 p230/an47/pwu_an7/out1_0/tioa26_0/pwm1m0 89 p231/an48/out2_0/tioa27_0/pwm2p0 90 p300/an49/out3_0/tioa28_0/pwm2m0 91 p301/an50/out4_0/tioa18_1/pwm1p1 92 p302/an51/tioa19_1/pwm1m1 93 p304/an52/text4_0/tioa20_1/pwm2p1 94 p305/an53/text5_0/tioa29_0/pwm2m1 97 p307/int1_0/an55/scs102_0/tiob18_0/pwm1p2 hi-z/input blocked *1 hi-z/input blocked *1 98 p308/an56/in0_1/tioa28_1/pwm1m2 99 p309/an57/in1_1/tioa29_1/pwm2p2 100 p312/an58/scs101_0/in2_1/tiob25_0/pwm2m2 101 p313/int10_1/an59/sot10_0/sda10_0/in3_1/tiob26_0/pwm1p3 hi-z/input blocked *1 hi-z/input blocked *1 102 p314/an60/sck10_0/scl10_0/in4_1/tiob27_0/tioa7_1/pwm1m3 103 p315/an61/tx1_1/scs100_0/in5_1/tiob28_0/tioa8_1/pwm2p3 104 p317/int11_1/an62/rx1_1/sin10_0/tiob29_0/tioa9_1/pwm2m3 hi-z/input blocked *1 hi-z/input blocked *1 107 p321/pwutrg hi-z/input blocked*8 (status immediately before the shutdown retaine) *6 (pwutrg output/input blocked *7) hi-z/input blocked *8 (last state retained) *6 (pwutrg output/inp ut blocked *7) hi-z/input blocked*8 (last state retained) *6 (pwutrg output/input blocked *7) hi-z/input blocked hi-z/input blocked*8 (last state retained) *3 *6 (*7) hi-z/input blocked 110 trst/p322 111 tdo/p323 112 tdi/p324 113 tms 114 tck 115 p327/wot with control hi-z /last status retained hi-z/input blocked status immediately before the shutdown retaine last state retained last state retained *3 hi-z/input blocked last state retained *3 hi-z/input blocked 116 nmix 117 md 118 x0 119 x1 121 p331/mcsx3/sga0_1 122 p400/mcsx2/sgo0_1 123 rstx - input enabled input enabled 127 p401/tx1_0/in0_0 hi-z/input blocked hi-z/input blocked 128 p402/int2_0/rx1_0/in1_0/v3 hi-z/input blocked *1 hi-z/input blocked *1 129 p403/in2_0/tracedata0/v2/sga1_1 130 p404/scs120_0/in3_0/tracedata1/mad14/v1/sgo1_1 131 p405/int11_0/sin12_0/in4_0/tracedata2/mad13/v0/sga2_1 hi-z/input blocked *1 hi-z/input blocked *1 132 p406/sot12_0/tracedata3/mad12/com0/sgo2_1 *9 133 p407/sck12_0/sck10_1/tracedata4/mad11/com1 *9 134 p408/sin2_0/tracedata5/tin18/mad10/com2 *9 135 p409/sot2_0/tioa24_1/tracedata6/tot18/mad09/com3 *9 136 p411/int13_1/sck2_0/scs101_1/tiob24_0/tracedata7/tin19/mad08/seg0 137 p413/int14_1/scs20_0/scs103_1/tot19/mad07/seg1 138 p414/scs21_0/tin32/mad06/seg2 139 p416/sin10_1/in5_0/tioa22_1/tot32/mad05/seg3 140 p417/int15_1/sot10_1/tioa23_1/tin33/mad04/seg4 141 p418/int14_0/scs22_0/tiob23_0/tot33/mad03/seg5 142 p420/sck2_1/traceclk/mad02/seg6 hi-z/input blocked *6 hi-z/input blocked *6 143 p421/int12_1/sin2_1/tracectl/mad01/seg7 hi-z/input blocked *1 *6 hi-z/input blocked *1 *6 timer mode *4 after external factor releasing external factor generation in progress after external factor releasing pin no. pin name gporten control external reset factor 1 external reset factor 2 external reset factor 3 with control hi-z/input blocked hi-z/ last status retained hi-z/input blocked hi-z/input blocked internal reset factor *2 sleep mode stop mode *4 hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked status immediately before the shutdown retaine last state retained last state retained *3 hi-z/input blocked last state retained *3 hi-z/input blocked hi-z/input blocked - hi-z/input blocked hi-z/input blocked hi-z/input blocked hi-z/input blocked input enabled (last state retained *7) input enabled (last state retained *3 *7) input enabled (hi-z/input blocked *7) input enabled (last state retained *3 *7) input enabled input enabled input enabled input enabled input enabled (status immediately before the shutdown retaine *7) - input enabled input enabled input enabled input enabled input enabled input enabled hi-z/input blocked hi-z/input blocked hi-z/input blocked input enabled (hi-z/input blocked *7) - - - - input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled - - - - - - - - with control hi-z/input blocked hi-z /last status retained hi-z/input blocked hi-z/input blocked hi-z/input blocked status immediately before the shutdown retaine last state retained last state retained *3 hi-z/input blocked last state retained *3 hi-z/input blocked input enabled input enabled input enabled input enabled input enabled input enabled with control hi-z/input blocked hi-z /last status retained hi-z /input blocked hi-z/input blocked hi-z/input blocked status immediately before the shutdown retaine last state retained last state retained *3 last state retained *3 hi-z/input blocked hi-z/input blocked output "l"/input blocked output "l"/ last status retained output "l"/ input blocked output "l"/ input blocked output "l"/ input blocked status immediately before the shutdown retaine *6 last state retained *3 *6 hi-z/input blocked *6 hi-z/input blocked *6 hi-z/input blocked *1 *6 hi-z/input blocked *1 *6 hi-z/input blocked *6 last state retained *3 *6 hi-z/input blocked *6 hi-z/input blocked hi-z /last status retained hi-z /input blocked hi-z /input blocked hi-z /input blocked hi-z/input blocked *1 *6 hi-z/input blocked *1 *6
document number: 002 - 04863 rev.*d page 48 of 141 s6j31 2 0 series *1 : input disable is not valid when external interrupts are enabled. *2 : recovery from standby (power off) becomes a factor. *3 : the pin state from the time that holdio_pd2 was set (sysc 0 _specfgr.holdio_pd2=1) is retained. if power - off has not occurred and holdio_pd2 has not been set (sysc 0 _specfgr.holdio_pd2=0), the last state is retained. *4 : to power off power domains 2 and 3, be sure to set holdio_pd2 (sysc 0 _specfgr.hold io_pd2=1). *5: the pin state when the port function is enabled is shown. *6: when port is used as lcd setting, pin state becomes the following. power domain 2 control power - off power - on mode - except pss main oscillation timer mode pss main oscillation timer mode main oscillation e nable setting - - enable (lcr0:lcen=1) disable (lcr0:lcen=0) pin state output "l" / input blocked output "l" / input blocked retention of lcd display output "l" / input blocked *7: when the pwu function is enabled, a change to output occurs. *8: when ppc_pcfgrijj:pof[2:0] is set to initial value. *9: when reset is issued, the following ports become "l" output as the initial state. - p019, p023, p024, p027, p028, p029, p030, p031, p100, p406, p407, p408, p409 therefore, don't add the pull - up registers outside of this product to the above ports. in case that the above ports are used as pull - up, use the pull - up function implemented in this product. - external reset factor 1 powe r - on reset (ponr) ram retention low - voltage detection reset (rvd) internal power supply low - voltage detection reset (lvdl1r) rstx pin + md pin simultaneous assert reset (initx) - external reset factor 2 rstx pin input reset (rstx) - external reset factor 3 hardware watchdog reset (hwdr) software watchdog reset (swdr) pll clock supervisor reset (csvprn) sscg clock supervisor reset (csvsrn) profile error reset (prferr) software trigger hard reset (shrst) software reset (srst)
document number: 002 - 04863 rev.*d page 49 of 141 s6j31 2 0 series - internal reset factor standby tra nsition reset / power domain reset
document number: 002 - 04863 rev.*d page 50 of 141 s6j31 2 0 series 10. e lectrical c haracteristics 10.1 absolute m aximum r atings parameter symbol rat ing unit remarks min max power supply voltage * 1 , * 2 v cc v ss - 0.3 v ss +6.0 v dv cc v ss - 0.3 v ss +6.0 v dv cc = v cc analog supply voltage * 1 , * 2 av cc v ss - 0.3 v ss +6.0 v a v cc = v cc analog reference vo ltage *1 avrh v ss - 0.3 v ss +6.0 v avrh av cc input voltage * 1 v i 1 v ss - 0.3 v cc +0.3 v v i 2 d v ss - 0.3 d v cc +0.3 v smc shared pin analog pin input voltage * 1 v ia 1 v ss - 0.3 v cc +0.3 v v ia 2 d v ss - 0.3 d v cc +0.3 v smc shared pin output voltage * 1 v o 1 v ss - 0.3 v cc +0.3 v v o 2 d v ss - 0.3 d v cc +0.3 v smc shared pin maximum clamp current | i clamp | - 4 ma * 8 total m aximum clamp current |i clamp | - 20 ma * 8 "l" - level maximum output current * 3 i ol1 - 3.5 ma when setting is 1 ma *6 i ol2 - 7 ma when setting is 2 ma i ol 3 - 40 ma when setting is 30 ma *7 "l" - level average output current * 4 i olav1 - 1 ma when setting is 1 ma *6 i olav2 - 2 ma when setting is 2 ma i olav 3 - 30 ma when setting is 30 ma *7 "l" - level total output current * 5 i ol 1 - 40 ma *6 i ol 2 - 15 0 ma * 7 "h" - level maximum output current * 3 i oh1 - - 3.5 ma when setting is 1 ma *6 i oh2 - - 7 ma when setting is 2 ma i oh 3 - - 40 ma when setting is 30 ma *7 "h" - level average output current * 4 i ohav1 - - 1 ma when setting is 1 ma *6 i ohav2 - - 2 ma when setting is 2 ma i ohav 3 - - 30 ma when setting is 30 ma *7 "h" - level total output current * 5 i oh 1 - - 40 ma *6 i oh 2 - - 15 0 ma * 7 power consumption p d - 20 00 mw s6j31 2 x h zc * 9 operating temperature t a - 40 +1 0 5 c storage temperature tstg - 55 +150 c *1 : these parameters are based on the condition that vss= dvss= avss=0.0v. *2: avcc, dvcc and vcc must be set to the same voltage. it is required that avcc and dvcc do not exceed vcc and that the voltage at the analog inputs does not exceed avcc when the power is switched on. *3 : the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *4 : the average output current is defined as the value of the average c urrent flowing through any one of the corresponding pins for a 10 ms period. the average value is the operation current x the operation ratio. *5 : the total output current is defined as the maximum current value flowing through all of corresponding pins. * 6 : corresponding pins: general - purpose ports * 7: corresponding pins: p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317
document number: 002 - 04863 rev.*d page 51 of 141 s6j31 2 0 series * 8: corresponding pins: all general - purpose ports and analog input pins. ? use the device within the recommended operating conditions. ? use the device with direct voltage (current). ? the + b signal should always be applied by connecting a limiting resistor between the + b signal and the microcontroller. ? the value of the limiting resistor should be set so that the curre nt input to the microcontroller pin does not exceed rated values at any time regardless of instantaneously or constantly when the + b signal is input. ? note that when the microcontroller drive current is low, such as in the low - power consumption modes, the + b input potential can increase the potential at the vcc pin via a protective diode, possibly affecting other devices. ? note that if the + b signal is input when the microcontroller is off (not fixed at 0 v), since the power is supplied through the pin, th e microcontroller may operate incompletely. ? note that if the +b signal is input at power - on, since the power is supplied through the pin, the power - on reset may not function in the power supply voltage. ? do not leave + b input pins open. *9: it is standard when four - layer substrate is used. example of a recommended circuit warning: ? semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. S6J3120 series
document number: 002 - 04863 rev.*d page 52 of 141 s6j31 2 0 series 10.2 recommended operating conditions (v ss = dv ss = av ss =0.0 v) parameter symbol value unit remarks min max supply voltage v cc 4.5 5. 5 v recommended operation assurance range d v cc 4.5 5. 5 v av cc 4.5 5.5 v v cc 3.5 5.5 v operation assurance range d v cc 3.5 5.5 v av cc 3.5 5.5 v smoothing capacitor * c s1 4.7 f tolerance of up to 40% , 126pin use a ceramic capacitor or a capacitor that has the similar frequency characteristics. use a capacitor with a capacitance greater than cs as the smoothing capacitor on the vcc pin. operating temperature t a - 40 +1 0 5 ? s6j31 2xhzc * * x:a/9/8, z:a/b * : for the connections of smoothing capacit or c s 1 , se e the following diagram. ? c pin connection diagram warning: 1. the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. 2. any use of semiconducto r devices will be under their recommended operating condition. 3. operation under any conditions other than these conditions may adversely affect reliability of device and could result in dev ice failure. 4. no warranty is made with respect to any use, operatin g conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. c s 1 c (126pin) v ss av ss v ss c (38pin) open
document number: 002 - 04863 rev.*d page 53 of 141 s6j31 2 0 series notes: ? the following condition should be satisfied in ord er to facilitate heat dissipation. 1. 4 or more layers pcb should be used. 2. the area of pcb should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (jedec standard) 3. 1 layer of middle layers at least should be used for dedicated layer to radiate heat with residual copper rate 90% or more. the layer can be used for system ground. 4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a part of 1 st layer. 5. t he part of 1 st layer should be connected to the dedicated heat radiation layer with more than 10 thermal via holes. figur e12.2 - 1: example thermal via holes on pcb. notes: ? figure 12.2 - 1 is a schematic diagram showing pcb in section. ? figure 12.2 - 2 in the following pages are recommended land patterns for each package series. thermal via holes should closely be placed and aligned with lands. ? if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002 - 04863 rev.*d page 54 of 141 s6j31 2 0 series figure 12.2 - 2 : land pattern and thermal via le u144
document number: 002 - 04863 rev.*d page 55 of 141 s6j31 2 0 series 10.3 dc characteristics (t a : recommended operating conditions, vcc =dvcc =5. 0 v 10%, v ss =dv ss =av ss =0.0 v) parameter symbo l pin name condition s value unit remarks min typ max "h" level input voltage ? v ih1 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p327, p331, p400 to p409, p411, p413 to p414, p416 to p4 18, p420 to p421 cmos schmitt ? input level selected 0.7v cc - v cc +0.3 v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 0.7 d v cc - d v cc +0.3 v
document number: 002 - 04863 rev.*d page 56 of 141 s6j31 2 0 series parameter symbo l pin name condition s value unit remarks min typ max "h" level input voltage v ih2 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p226, p327 to p331 p400 to p409, p411, p413 to p414, p416 to p418, p420 to p421 automotive input level sel ected 0.8v cc - v cc +0.3 v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 0.8 d v cc - d v cc +0.3 v v ih4 rstx, nmix - 0.7v cc - v cc +0.3 v v ih5 md - 0.7v cc - v cc +0.3 v v ih6 trst, tck, tdi, tms ttl input level 2. 3 - v cc +0.3 v
document number: 002 - 04863 rev.*d page 57 of 141 s6j31 2 0 series parameter symbo l pin name condition s value unit remarks min typ max "l" level input voltage v il1 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p327 to p331, p400 to p409, p411, p413 to p414, p416 to p418, p420 to p421 cmos schmitt input level selected vss - 0.3 - 0.3v cc v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vss - 0.3 - 0.3 d v cc v
document number: 002 - 04863 rev.*d page 58 of 141 s6j31 2 0 series parameter symbo l pin name condition s value unit remarks min typ max "l" level input voltage v il2 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p226, p327, p331 p40 0 to p409, p411, p413 to p414, p416 to p418, p420 to p421 automotive input level selected vss - 0.3 - 0.5v cc v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vss - 0.3 - 0.5 d v cc v v il4 rstx, nmix - vss - 0.3 - 0.3v cc v v il5 md - vss - 0.3 - 0.3v cc v v il6 trst, tck, tdi, tms ttl input level vss - 0.3 - 0.8 v
document number: 002 - 04863 rev.*d page 59 of 141 s6j31 2 0 series (t a : recommended operating conditions, vcc =dvcc =5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symb ol pin name condition s value unit remarks min typ max "h" level output voltage v oh1 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p321 to p324, p327, p331, p400 to p40 1 , p403 to p409, p411, p413 to p414, p416 to p418, p420 to p421 vcc=4.5 v i oh = - 2.0 ma vcc - 0.5 - vcc v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vcc=4.5 v i oh = - 2.0 ma d vcc - 0.5 - d vcc v
document number: 002 - 04863 rev.*d page 60 of 141 s6j31 2 0 series parameter symb ol pin name condition s value unit remarks min typ max "h" level output voltage v oh2 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p321 to p324, p327, p331, p400 to p401, p403 to p409, p411, p413 to p414, p416 to p418, p420 to p421 vcc=4.5 v i oh = - 1.0 ma vcc - 0.5 - vcc v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vcc=4.5 v i oh = - 1.0 ma d vcc - 0.5 - d vcc v "h" level output voltage v oh3 p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vcc=4.5 v i oh = - 30 .0 ma d vcc - 0.5 - d vcc v
document number: 002 - 04863 rev.*d page 61 of 141 s6j31 2 0 series parameter symb ol pin name condition s value unit remarks min typ max "l" level output voltage v ol1 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p321 to p324, p327, p331, p400 to p401 p403 to p409, p411, p413 to p414, p416 to p418, p420 to p421 vcc=4.5 v i ol =2.0 ma 0 - 0.4 v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vcc=4.5 v i ol =2.0 ma 0 - 0.4 v "l" level output voltage v ol2 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p321 to p324, p327, p331, p400 to p401 p403 to p409, p411, p413 to p414, p416 to p418, p420 to p421 vcc=4.5 v i ol =1.0 ma 0 - 0.4 v p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vcc=4.5 v i ol =1.0 ma 0 - 0.4 v
document number: 002 - 04863 rev.*d page 62 of 141 s6j31 2 0 series parameter symb ol pin name condition s value unit remarks min typ max "l" level output voltage v ol3 p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 d vcc=4.5 v i ol = 30 .0 ma 0 - 0. 55 v
document number: 002 - 04863 rev.*d page 63 of 141 s6j31 2 0 series (t a : recommended operating conditions, vcc =dvcc =5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name conditions value unit remarks min typ max input leakage current i il all input pins v cc = dv cc = av cc =5. 5 v v ss < vi < v cc - 5 - +5 a pull - up resistor r up1 rstx, nmix - 25 - 100 k up2 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 p327, p331, p400 to p409, p411, p413 to p414, p416 to p418, p420 to p421 pull - up resistor selected 25 - 100 k up3 tdi(p324), tms, tck - 25 - 100 k
document number: 002 - 04863 rev.*d page 64 of 141 s6j31 2 0 series parameter symbol pin name conditions value unit remarks min typ max pull - down resistor r down1 p000 to p001, p003, p005 to p010, p012 to p013, p015 to p024, p027 to p031, p100 to p101, p103, p105 to p109, p112 to p115, p117 to p120, p122 to p123, p126 to p131, p202 to p215, p218 to p220, p222 to p2 26 , p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 p327, p331, p400 to p409, p411, p413 to p414, p416 to p418, p420 to p421 pull - down resistor selected 25 - 100 k r down2 trst(p322) - 25 - 100 k input capac itance c in pins other than vcc, vss, avcc0, avcc1, avss0, avss1 - - 5 15 pf
document number: 002 - 04863 rev.*d page 65 of 141 s6j31 2 0 series (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) paramet er symbol pin name conditions value unit remarks mi n typ max power supply current s6j31 2 x h zc * *x:a/9/8 z: a/b i cc5 vcc normal operation - 90 195 ma operating at 1 28 mhz flash write/erase - 125 255 ma operating at 1 28 mhz i ccs5 cpu sleep - 60 160 ma operating at 1 28 mhz i cct5 timer mode - 4 80 14 50 a t a =25 ? c slow - cr source oscillation i cct5m timer mode (main osc) - 1340 2525 a t a =25 ? c main source oscillation * i cch5 stop mode - 4 80 14 50 a t a =25 ? c i ccp pwu mode (shutdown) - 52.5 129.7 a t a =25 ? (pwu operation cycle 16ms) - 46.2 115.5 a t a =25 ? (pwu operation cycle 32ms) i cct52 timer mode (shutdown) - 40 100 a t a =25 ? c slow - cr source oscillation i cct52m timer mode (main osc) (shut down) - 350 520 a t a =25 ? c main source oscillation * i cch52 stop mode (shutdown) - 40 100 a t a =25 ? c refer t o hardware manual " a ppendix state t ransition " for in ternal clock frequency setting / setting of the power domain / regulator setting . *: the external load capacitance connected to x0/x1 is considerd as 10pf .
document number: 002 - 04863 rev.*d page 66 of 141 s6j31 2 0 series (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbo l pin name conditions value unit remarks min typ max high current output drive capacity phase to phase deviation1 oh3 pwm1pn, pwm1mn, pwm2pn, pwm2mn (n=0 to 3) dv cc =4.5v i oh = - 30.0ma maximum deviation of v oh3 - - 90 mv * high current output drive capacity phase to phase deviation 2 o l 3 pwm1pn, pwm1mn, pwm2pn, pwm2mn (n=0 to 3) dv cc =4.5v i oh = - 30.0ma maximum deviation of v o l 3 - - 90 mv * lcd divider resistor r lcd v0 to v1, v1 to v2, v2 to v3 - 6.25 12.5 25 k com0 to com3 output impedance r vcom comm (m=0 to 3) - - - 4.5 k seg00 to seg31 output impedance r vseg segn (n=00 to 31) - - - 17 k lcdc leak current i lcdc v0 to v3, comm (m=0 to 3) segn (n=00 to 31) t a =25 ? *: if pwm1p0/pwm1m0/pwm2p0/pwm2m0 of ch.0 is turned on simultaneously, the maximum deviation of voh3/vol3 for each pin is defined. same for other channels.
document number: 002 - 04863 rev.*d page 67 of 141 s6j31 2 0 series 10.4 ac characteristics 10.4.1 source clock timing (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name con ditio ns value unit remarks min typ max source oscillation clock frequency f c x0, x1 - - 4 - mhz source oscillation clock cycle time t cyl x0, x1 - - 250 - ns can pll jitter ( during lock ) t pj - - - 10 - +10 ns * built - in slow - cr oscillation frequency f crs - - 50 100 150 khz built - in fast - cr oscillation frequency f crf - - 2.4 4 6.0 mhz pll input clock frequency f plli - - - 4 - mhz pll macro oscillation clock frequency f pllo - - 400 - 5 12 mhz sscg - pll input clock frequency f sscgplli - - - 4 - mhz sscg - pll macro oscillation clock frequency f sscgpllo - - 400 - 5 12 mhz * : the maximum/minimum values have been standardized with the main clock and pll clock in use. ? x0 and x1 clock timing x0 t cyl
document number: 002 - 04863 rev.*d page 68 of 141 s6j31 2 0 series ? can pll jitter a time difference from the ideal clock is guaranteed for each cycle period within 20,000 cycles. slow fast ideal clock pll output
document number: 002 - 04863 rev.*d page 69 of 141 s6j31 2 0 series 10.4.2 internal clock timing (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name conditions s6j31 2x h zc * value * x:a/9/8, z:a/b unit remarks min typ max internal clock frequency f clk_cpu - - - - 128 mhz clk_cpu f clk_fclk - - - - 64 mhz clk_fclk f clk_atb - - - - 64 mhz clk_atb f clk_dbg - - - - 64 mhz clk_dbg f clk_hpm - - - - 32 mhz clk_hpm f clk_hpm2 - - - - 16 mhz clk_hpm2 f clk_dma - - - - 32 mhz clk_dma f clk_memc - - - - 32 mhz clk_memc f clk_extbus - - - - 25 mhz clk_extbus f clk_sysc1 - - - - 32 mhz clk_sysc1 f clk_happ0a0 - - - - 32 mhz clk_happ0a0 f clk_happ0a1 - - - - 32 mhz clk_happ0a1 f clk_happ1b0 - - - - 32 mhz clk_happ1b0 f clk_happ1b1 - - - - 32 mhz clk_happ1b1 f clk_llpbm - - - - 128 mhz clk_llpbm f clk_llpbm2 - - - - 64 mhz clk_llpbm2 f clk_lcp - - - - 64 mhz clk_lcp f clk_lcp0 - - - - 32 mhz clk_lcp0 f clk_lcp0a - - - - 32 mhz clk_lcp0a f clk_lcp1 - - - - 32 mhz clk_lcp1 f clk_lcp1a - - - - 32 mhz clk_lcp1a f clk_lapp0 - - - - 32 mhz clk_lapp0 f clk_lapp0a - - - - 32 mhz clk_lapp0a f clk_lapp1 - - - - 32 mhz clk_lapp1 f clk_lapp1a - - - - 32 mhz clk_lapp1a f clk_trc - - - - 64 mhz clk_trc f clk_hsspi - - - - 32 mhz clk_hsspi f clk_sysc0h - - - - 32 mhz clk_sysc0h f clk_comh - - - - 32 mhz clk_comh f clk_ram0h - - - - 32 mhz clk_ram0h f clk_ram1h - - - - 32 mhz clk_ram1h f clk_sysc0p - - - - 32 mhz clk_sysc0p f clk_comp - - - - 32 mhz clk_comp f c anfd _c clk - - - - 40 mhz c anfd _c clk
document number: 002 - 04863 rev.*d page 70 of 141 s6j31 2 0 series parameter symbol pin name conditions s6j31 2x h zc * value * x:a/9/8, z:a/b unit remarks min typ max internal clock cycle time t clk_cpu - - 7.82 - - ns clk_cpu t clk_flash - - 15.64 - - ns clk_fclk t clk_atb - - 15.64 - - ns clk_atb t clk_dbg - - 15.64 - - ns clk_dbg t clk_hpm - - 31.28 - - ns clk_hpm t clk_hpm2 - - 62.54 - - ns clk_hpm2 t clk_ d ma - - 31.28 - - ns clk_dma t clk_memc - - 31.28 - - ns clk_memc t clk_extbus - - 40 .00 - - ns clk_extbus t clk_sysc1 - - 31.28 - - ns clk_sysc1 t clk_happ0a0 - - 31.28 - - ns clk_happ0a0 t clk_happ0a1 - - 31.28 - - ns clk_happ0a1 t clk_happ1b0 - - 31.28 - - ns clk_happ1b0 t clk_happ1b1 - - 31.28 - - ns clk_happ1b1 t clk_llpbm - - 7.82 - - ns clk_llpbm t clk_llpbm2 - - 15.64 - - ns clk_llpbm2 t clk_lcp - - 15.64 - - ns clk_lcp t clk_lcp0 - - 31.28 - - ns clk_lcp0 t clk_lcp0a - - 31.28 - - ns clk_lcp0a t clk_lcp1 - - 31.28 - - ns clk_lcp1 t clk_lcp1a - - 31.28 - - ns clk_lcp1a t clk_lapp0 - - 31.28 - - ns clk_lapp0 t clk_lapp0a - - 31.28 - - ns clk_lapp0a t clk_lapp1 - - 31.28 - - ns clk_lapp1 t clk_lapp1a - - 31.28 - - ns clk_lapp1a t clk_trc - - 15.64 - - ns clk_trc t clk_hsspi - - 31.28 - - ns clk_hsspi t clk_sysc0h - - 31.28 - - ns clk_sysc0h t clk_comh - - 31.28 - - ns clk_comh t clk_ram0h - - 31.28 - - ns clk_ram0h t clk_ram1h - - 31.28 - - ns clk_ram1h t clk_sysc0p - - 31.28 - - ns clk_sysc0p t clk_comp - - 31.28 - - ns clk_comp t c anfd _c clk - - 25 .00 - - ns c anfd _c clk
document number: 002 - 04863 rev.*d page 71 of 141 s6j31 2 0 series ? guaranteed operation range internal operation clock frequency vs. power supply voltage note: a supply voltage that is equal to or less than the set voltage for low - voltage detection causes a reset. 2 4 128 internal clock frequency f c pu _clk (mhz) 3.5
document number: 002 - 04863 rev.*d page 72 of 141 s6j31 2 0 series relationship between the oscillation clock frequency and internal clock frequency oscillation clock frequency main clock pll multiplier setting pll output division setting pll clock 4 mhz 4 mhz 1 2 8 4 12 8 mhz 4 mhz 4 mhz 120 6 80 mhz ? oscillation circuit example note s : ? w hen configuring the oscillator circuit, it is recommended to ask matching evaluation of the circuit to oscillator manufacturers for the design. ? the maximum pll clock frequency must be 1 28 mhz. output division configuration can be set by the following. - plldivm bit in sysc0_runpll0cntr register - plldivm bit in sysc0_psspll0cntr register - sscgdivm bit in sysc0_runsscg0cntr0 register - sscgdivm bit in sysc0_psssscg0cntr0 register (e.g. if pllout is 448 mhz, these settings must be configured as "multiply by 4 " and over multiplication setting) ac characteristics are specified by the following measurement reference voltage values. ? input signal waveform ? output signal waveform hysteresis input pin (automotive) output pin hysteresis input pin (cmos schmitt) hysteresis input pin (ttl) x1 x0 r c 2 c 1 0. 5 vcc 0.8vcc 0.8v 2.4v 0.3vcc 0.7vcc 0. 8 v 2.0 v
document number: 002 - 04863 rev.*d page 73 of 141 s6j31 2 0 series 10.4.3 reset input (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name conditions value unit remarks min max reset input time t rstl rstx - 10 - s width for reset input removal 1 - s rstx 0. 2 vcc 0. 2 vcc t rstl
document number: 002 - 04863 rev.*d page 74 of 141 s6j31 2 0 series 10.4.4 power - on conditions (t a : recommended operating conditions, v ss =0.0 v) parameter symbol pin name condition s value unit remarks min typ max level detection voltage - vcc - 2. 1 5 2. 3 5 2. 5 5 v level detection hysteresis width - vcc - - 100 - mv level detection time - - - - - 540 s C C C C *1: if a power fluctuation precedes the low - voltage detection time, the detection may occur or be canceled after the supply voltage passes the detection voltage range. *2: if v cc is held below 0.2v for a minimum period of toff, power - on reset will occur. if toff is not satisfied, power - on reset will still occur if the power ramp rate is kept below 6mv/s. *3: this is the power ramp rate with which power - on reset will always occur regardless of power - off time, as mentioned in *2. *4: when vcc is within 2.6v - 4.5v, and vcc fluctuation is below 50mv/us, the power - on reset is suppressed. between 4.5v - 5.5v, the power - on reset does not occur with any vcc fluctuation. note: when neither *2 nor *3 can be satisfied, assert external reset (rstx) at power - up and at any brownout ev ent. ? power off time, power ramp rate at power - on ? v cc t off 0.2v 0.2v dv/dt v cc 2 . 6 v | dv/dt | 5.5v | dv/dt | 4.5v
document number: 002 - 04863 rev.*d page 75 of 141 s6j31 2 0 series 10.4.5 clock output timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) ( external load capacitance 16pf ) parameter symbo l pin name conditions value unit remarks min max cycle time t cyc mclk 2ma is selected in odr bit in ppc_pcfg r register. 40 - ns clock high width *1 t chcl mclk d h t cyc - 7 d h t cyc + 7 ns clock low width *2 t clch mclk d l t cyc - 7 d l t cyc + 7 ns * 1 : if division - ratio is even value, d h is equivalent to 0.5. otherwise, d h is calculated as the following. d h = the number rounding " division - ratio x 0.5 " down to the nearest integer / division - ratio division - ratio is multiplication value among sysdiv bit, hpmdiv bit and extbusdiv bit setting. ex). setting sysdiv to 1 - division, hpmdiv to 7 - division, ex t busdiv to 1 - division, d h is calculated as 0.429. * 2 : if division - ratio is even value, d l is equivalent to 0.5. otherwise, d l is calculated as the following. d l = the number rounding " division - ratio x 0.5 " up to the nearest integer / division - ratio division - ratio is multiplication value among s ysdiv bit, hpmdiv bit and extbusdiv bit setting. ex). setting sysdiv to 1 - division, hpmdiv to 7 - division, ex t busdiv to 1 - division, d l is calculated as 0.571. ? clock out put timing
document number: 002 - 04863 rev.*d page 76 of 141 s6j31 2 0 series 10.4.6 external bus interface timing 10.4.6.1 common timing between read and write (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) ( external load capacitance 16pf ) parameter symbo l pin name conditions value unit remarks min max cycle time (without mrdy) t cyc mclk 2ma is selected in odr bit in ppc_pcfgr register. 40 - ns cycle time (with mrdy) t cyc mclk 50 - ns if using mrdy, set mclk to 20mhz or less. cs delay time t cso mclk, mcsx0 to mcsx3 0.5 18 ns address delay time t ao mclk, mad00 to mad23 0.5 18 ns rdy setup time t rdys mclk, mrdy " cmos schmitt input " and " disable noise filter " are selected in ppc_pcfgr register. 21 - ns rdy hold time t rdyh mclk, mrdy 0 - ns ? external bus i/f common timing
document number: 002 - 04863 rev.*d page 77 of 141 s6j31 2 0 series 10.4.6.2 read timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) ( external load capacitance 16pf ) parameter symbo l pin name conditions value unit remarks min max data setup time t dsr moex, mdata00 to mdata15 " cmos schmitt input " and " disable noise filter " are selected in ppc_pcfgr register. 21+ t cy c - ns data hold time t dhr moex, mdata00 to mdata15 0 - ns moex delay time t rdo mclk, moex 2ma is selected in odr bit in ppc_pcfgr register. 0.5 18 ns ? external bus i/f read timing
document number: 002 - 04863 rev.*d page 78 of 141 s6j31 2 0 series 10.4.6.3 write timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) ( external load capacitance 16pf ) parameter symbo l pin name conditions value unit remarks min max mwex delay time t weo mclk, mwex 2ma is selected in odr bit in ppc_pcfgr register. 0.5 18 ns byte mask delay time t wro mclk, mdqm0 to mdqm1 0.5 18 ns data delay time t do mclk, mdata00 to mdata15 0.5 18 ns data delay time (hi - z output) t doz mclk, mdata00 to mdata15 - 18 ns ? external bus i/f write timing
document number: 002 - 04863 rev.*d page 79 of 141 s6j31 2 0 series 10.4.7 multi - function serial 10.4.7.1 csio timing (smr:md [2:0] =010 b ) (5 - 1 - 1) normal synchronous transfer (scr:spi=0) and serial clock output signal detect level "h" (smr:scinv=0) (t a : recommended operating conditions, vcc =dvcc =5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck 4, sck8 to sck12 master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 4 t clk_lcp n a * - ns sck t slovi sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 +30 ns valid sin t ivshi sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 30 - ns sck t shixi 0 - ns serial clock "h" pulse width t shsl sck0 to sck 4, sck8 to sck12 slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a * +10 - ns serial clock "l" pulse width t slsh 2 t clk_lcp n a * - 10 - ns sck t slove sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 ns valid sin t ivshe sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 10 - ns sck t shixe 20 - ns sck fall time t f sck0 to sck 4, sck8 to sck12 - 5 ns sck ris e time t r sck0 to sck 4, sck8 to sck12 - 5 ns *: n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12 note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002 - 04863 rev.*d page 80 of 141 s6j31 2 0 series master mode t scyc v ol t slovi t ivshi t shixi v ih v il v oh v ol sck sot sin v ih v il v oh slave mode t slsh v i l t slove t ivshe t shixe v ih v il v oh v ol sck sot sin v ih v il t f v ih v i l v ih t shsl t r v ih
document number: 002 - 04863 rev.*d page 81 of 141 s6j31 2 0 series (5 - 1 - 2) normal synchronous transfer (scr:spi=0) and serial clock output signal detect level "l" (smr:scinv=1) (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck 4, sck8 to sck12 master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 4 t clk_lcp n a * - ns sck t shovi sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 +30 ns valid sin t ivsli sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 30 - ns sck t slixi 0 - ns serial clock "h" pulse width t shsl sck0 to sck 4, sck8 to sck12 slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a * +10 - ns serial clock "l" pulse width t slsh 2 t clk_lcp n a * - 10 - ns sck t shove sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 ns valid sin t ivsle sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 10 - ns sck t slixe 20 - ns sck fall time t f sck0 to sck 4, sck8 to sck12 - 5 ns sck ris e time t r sck0 to sck 4, sck8 to sck12 - 5 ns *: n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12 note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002 - 04863 rev.*d page 82 of 141 s6j31 2 0 series master m ode master mode t scyc v oh t shovi t ivsli t slixi v ih v il v o h v ol sck sot sin v ih v il v ol slave mode slave mode t shsl v i l t shove t ivsle t slixe v ih v il v oh v ol sck sot sin v ih v il t r v ih v i l v ih t slsh t f v i l
document number: 002 - 04863 rev.*d page 83 of 141 s6j31 2 0 series (5 - 1 - 3) spi supported (scr:spi=1), and serial clock output signal detect level "h" (smr:scinv=0) (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck 4, sck8 to sck12 master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 4 t clk_lcp n a * - ns sck t shovi sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 +30 ns valid sin t ivsli sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 30 - ns sck t slixi 0 - ns sot t sovli sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 2 t clk_lcp n a * - 30 - ns serial clock "h" pulse width t shsl sck0 to sck 4, sck8 to sck12 slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a * +10 - ns serial clock "l" pulse width t slsh 2 t clk_lcp n a * - 10 - ns sck t shove sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 ns valid sin t ivsle sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 10 - ns sck t slixe 20 - ns sck fall time t f sck0 to sck 4, sck8 to sck12 - 5 ns sck ris e time t r sck0 to sck 4, sck8 to sck12 - 5 ns *: n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12 note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002 - 04863 rev.*d page 84 of 141 s6j31 2 0 series master mode t scyc v ol t sovli t slixi v ih v il v oh v ol sck sot sin v ih v il v oh v oh v ol t ivsli t sho vi v ol slave mode t slsh v i l t f t slixe v ih v il v oh v ol sck sot sin v ih v il v ih v o h v ol t ivsle t shov e v i l v ih v ih v i l t shsl t r * * changes when writing to the tdr register
document number: 002 - 04863 rev.*d page 85 of 141 s6j31 2 0 series (5 - 1 - 4) spi supported (scr:spi=1), and serial clock output signal detect level "l" (smr:scinv=1) (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symb ol pin name conditions value unit remarks min max serial clock cycle time t scyc sck0 to sck 4, sck8 to sck12 master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 4 t clk_lcp n a * - ns sck t slovi sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 +30 ns valid sin t ivshi sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 30 - ns sck t shixi 0 - ns sot t sovhi sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 2 t clk_lcp n a * - 30 - ns serial clock "h" pulse width t shsl sck0 to sck 4, sck8 to sck12 slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a * +10 - ns serial clock "l" pulse width t slsh 2 t clk_lcp n a * - 10 - ns sck t slove sck0 to sck 4 , sck8 to sck12, sot0 to sot 4, sot8 to sot12 - 30 ns valid sin t ivshe sck0 to sck 4 , sck8 to sck12, sin0 to sin 4, sin8 to sin12 10 - ns sck t shixe 20 - ns sck fall time t f sck0 to sck 4, sck8 to sck12 - 5 ns sck ris e time t r sck0 to sck 4, sck8 to sck12 - 5 ns *: n= 0 :ch.0 to ch. 4, n=1:ch.8 to ch.12 note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002 - 04863 rev.*d page 86 of 141 s6j31 2 0 series master mode t scyc v oh t sovh i t shixi v ih v il v oh v ol sck sot sin v ih v il v ol v oh v ol t ivshi t slovi v oh slave mode t shsl v i l t r t shixe v ih v il v oh v ol sck sot sin v ih v il v ih v oh v ol t ivshe t slo v i l v ih v ih v i l t slsh t f * * changes when writing to the tdr register
document number: 002 - 04863 rev.*d page 87 of 141 s6j31 2 0 series (5 - 1 - 5) serial chip select used (scscr:csen=1) ? mark level "h" of serial clock output (smr, scsfr:scinv=0) ? inactive level "h" of serial chip select (scscr, scsfr:cslvl=1) (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name condition s value unit remarks min max scs t cssi sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t cssu * 1 - 50 - ns sck t cshi t cshd * 2 +0 - ns scs deselect time t csdi scs0x to scs 4 x , scs8x to scs12x t csds * 3 - 50 +5 t clk_lcp n a * 4 - ns scs t csse sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +30 - ns sck t cshe 0 - ns scs deselect time t csde scs0x to scs 4 x , scs8x to scs12x 3 t clk_lcp n a * 4 +30 - ns scs t dse scs0x to scs 4 x , scs8x to scs12x, sot0 to sot 4, sot8 to sot12 - 40 ns scs t dee 0 - ns sck t scc sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode round operation (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +0 3 t clk_lcp n a * 4 +50 ns *1 : t cssu =scstr:cssu [ 7 :0] x serial chip select timing operating clock *2 : t cshd =scstr:cshd [ 7 :0] x serial chip select timing operating clock *3 : t csds =scstr:csds [ 15 : 0 ] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12
document number: 002 - 04863 rev.*d page 88 of 141 s6j31 2 0 series note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi sc s output t cshi t csdi v ol v ol v ol v oh v oh v oh slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v il v il v ih v ih v il v ih v ol v ol v oh
document number: 002 - 04863 rev.*d page 89 of 141 s6j31 2 0 series clock switching example by master mode round operation (x,y = 0,1,2,3 ,4,8,9,10,11,12 : x and y are different value ) scsy output sck output scsx output t scc v ol v ol
document number: 002 - 04863 rev.*d page 90 of 141 s6j31 2 0 series (5 - 1 - 6) serial chip select used (scscr:csen=1) ? serial clock output signal detect level "l" (smr, scsfr:scinv=1) ? serial chip select inactive level "h" (scscr, scsfr:cslvl=1) (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) p arameter symbol pin name condition s value unit remarks min max scs t cssi sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t cssu * 1 - 50 - ns sck t cshi t cshd * 2 +0 - ns scs deselect ti me t csdi scs0x to scs 4 x , scs8x to scs12x t csds * 3 - 50+5 t clk_lcp n a * 4 - ns scs t csse sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +30 - ns sck t cshe 0 - ns scs deselect time t csde scs0x to scs 4 x , scs8x to scs12x 3 t clk_lcp n a * 4 +30 - ns scs t dse scs0x to scs 4 x , scs8x to scs12x, sot0 to sot 4, sot8 to sot12 - 40 ns scs t dee 0 - ns sck t scc sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode round operation (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +0 3 t clk_lcp n a * 4 +50 ns *1 : t cssu =scstr:cssu [ 7 :0] x serial chip select timing operating clock *2 : t cshd =scstr:cshd [ 7 :0] x serial chip select timing operating clock *3 : t csds =scstr:csds [ 15 :0] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12
document number: 002 - 04863 rev.*d page 91 of 141 s6j31 2 0 series note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance app lied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual. master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi scs output t csh i t csd i v ol v ol v oh v oh v oh v ol slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v il v il v ih v ih v ih v il v o l v o l v oh
document number: 002 - 04863 rev.*d page 92 of 141 s6j31 2 0 series clock switching example by master mode round operation (x,y= 0,1,2,3 ,4,8,9,10,11,12 : x and y are different value ) scsy output sck output scsx output t scc v ol v oh
document number: 002 - 04863 rev.*d page 93 of 141 s6j31 2 0 series (5 - 1 - 7) serial chip select used (scscr:csen=1) ? serial clock output signal detect level "h" (smr, scsfr:scinv=0) ? serial chip select inactive level "l" (scscr, scsfr:cslvl=0 (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symb ol pin na me conditions value unit remarks min max scs t cssi sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t cssu * 1 - 50 - ns sck t cshi t cshd * 2 +0 - ns scs deselect time t csdi scs0x to scs 4 x , scs8x to scs12x t csds * 3 - 50+5 t clk_lcp n a * 4 - ns scs t csse sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +30 - ns sck t cshe 0 - ns scs deselect time t csde scs0x to scs 4 x , scs8x to scs12x 3 t clk_lcp n a * 4 +30 - ns scs t dse scs0x to scs 4 x , scs8x to scs12x, sot0 to sot 4, sot8 to sot12 - 40 ns scs t dee 0 - ns sck t scc sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode round operation (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +0 3 t clk_lcp n a * 4 +50 ns *1 : t cssu =scstr:cssu [ 7 :0] x serial chip select timing operating clock *2 : t cshd =scstr:cshd [ 7 :0] x serial chip select timing operating clock *3 : t csds =scstr:csds [ 15 : 0 ] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12
document number: 002 - 04863 rev.*d page 94 of 141 s6j31 2 0 series note s : ? this is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rat e is limited by the internal operating clock used and other parameters. for details, see the hardware manual
document number: 002 - 04863 rev.*d page 95 of 141 s6j31 2 0 series clock switching example by master mode round operation (x,y=0,1,2 : x and y are different value.) scsy output s ck output scsx output t scc slave mode sck input s ot (normal sync transfer) s ot (spi compatible) t csse scs input t cshe t csde t dse t dee v ih v ih v i l v ih v i l master mode sck output s ot (normal sync transfer) s ot (spi compatible) t cssi scs output t cshi t csdi v oh v o l v oh v oh v o l v o l v o l v oh v o l v o
document number: 002 - 04863 rev.*d page 96 of 141 s6j31 2 0 series (5 - 1 - 8) serial chip select used (scscr:csen=1) ? serial clock output signal detect level "l" (smr, scsfr:scinv=1) ? serial chip select inactive level "l" (scscr, scsfr:cslvl=0) (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name condition s value unit remarks min max scs t cssi sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t cssu * 1 - 50 - ns sck t cshi t cshd * 2 +0 - ns scs deselect time t csdi scs0x to scs 4 x , scs8x to scs12x t csds * 3 - 50+5 t clk_lcp n a * 4 - ns scs t csse sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x slave mode (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +30 - ns sck t cshe 0 - ns scs deselect time t csde scs0x to scs 4 x , scs8x to scs12x 3 t clk_lcp n a * 4 +30 - ns scs t dse scs0x to scs 4 x , scs8x to scs12x, sot0 to sot 4, sot8 to sot12 - 40 ns scs t dee 0 - ns sck t scc sck0 to sck 4 , sck8 to sck12, scs0x to scs 4 x , scs8x to scs12x master mode round operation (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) 3 t clk_lcp n a * 4 +0 3 t clk_lcp n a * 4 +50 ns *1 : t cssu =scstr:cssu [ 7 :0] x serial chip select timing operating clock *2 : t cshd =scstr:cshd [ 7 :0] x serial chip select timing operating clock *3 : t csds =scstr:csds [ 15 : 0 ] x serial chip select timing operating clock for details on *1 , *2 , and *3 above, see the hardware manual. *4 t clk_lcpna n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12
document number: 002 - 04863 rev.*d page 97 of 141 s6j31 2 0 series note s : ? th is is the ac characteristic in clk synchronized mode. ? cl is the load capacitance applied to pins during testing. ? the maximum baud rate is limited by the internal operating clock used and other parameters. for details, see the hardware manual.
document number: 002 - 04863 rev.*d page 98 of 141 s6j31 2 0 series master mode sck output sot (normal synchronous transfer) sot (spi compatible ) t cssi scs output t cshi t csdi v oh v oh v ol v ol v oh v ih slave mode sck input sot (normal synchronous transfer) sot (spi compatible ) t csse scs input t cshe t csde t dse t dee v ih v il v il v ol v ol v oh clock switching example by master mode round operation (x,y= 0,1,2,3 ,4,8,9,10,11,12 : x and y are different value ) scsy output sck output scsx output t scc v oh v oh
document number: 002 - 04863 rev.*d page 99 of 141 s6j31 2 0 series 10.4.7.2 uart ( async serial interface ) timing (smr:md [2:0] =000 b , 001 b ) (5 - 2 - 1) external clock selected (bgr:ext=1) (t a : recommended operating conditions, vcc =dvcc =5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name condition s value unit remarks min ma x serial clock "l" pulse width t slsh sck0 to sck 4, sck8 to sck12 (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a * +10 - ns serial clock "h" pulse width t shsl t clk_lcp n a * +10 - ns sck fall time t f - 5 ns sck ris e time t r - 5 ns *: n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12 external clock selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il
document number: 002 - 04863 rev.*d page 100 of 141 s6j31 2 0 series 10.4.7.3 lin interface (v2.1) (lin communication control interface (v2.1)) timing (smr:md [ 2 : 0 ] =011 b ) (5 - 3 - 1) external clock selected (bgr:ext=1) (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name condition s value unit remarks min max serial clock "l" pulse width t slsh sck0 to sck 4, sck8 to sck12 (cl=50pf, i ol = - 2ma, i oh =2ma), (cl=20pf, i ol = - 1ma, i oh =1ma) t clk_lcp n a * +10 - ns serial clock "h" pulse width t shsl t clk_lcp n a * +10 - ns sck fall time t f - 5 ns sck ris e time t r - 5 ns *: n=0:ch.0 to ch. 4, n=1:ch.8 to ch.12 external clock selected sck t shsl v il v ih v ih t r t slsh t f v il v ih v il
document number: 002 - 04863 rev.*d page 101 of 141 s6j31 2 0 series 10.4.7.4 i 2 c timing (smr:md[2:0]=100b) (t a : recommended operating conditions, vcc=5.0 v +5%/ - 10%, v ss =av ss =0.0 v) parameter symbol pin name conditions standard mode unit remarks min max scl clock frequency f scl scl0 , scl3, scl4, scl8 to scl1 1 c l =50pf, r=(vp/i ol ) *1 0 100 khz repeat "start" condition hold time sda scl t hdsta sda0 , sda3, sda 4, sda8 to sda1 1 scl0 , scl3, scl 4, scl8 to scl1 1 4.0 - s period of "l" for scl clock t low scl0, scl3, scl4, scl8 to scl1 1 4.7 - s period of "h" for scl clock t high 4.0 - s repeat "start" condition setup time scl sda t susta sda0 , sda3, sda 4, sda8 to sda11 scl0 , scl3, scl 4, scl8 to scl11 4.7 - s data hold time scl sda t hddat 0 3.45 *2 s data setup time sda scl t sudat 250 - ns "stop" condition setup time scl sda t susto 4.0 - s bus - free time between "stop" condition and "start" condition t buf - 4.7 - s noise filter t sp - t nft * 3 - ns *1 : r and cl represent the pull - up resistance and load capacitance of the scl and sda output lines, respectively vp shows that the power - supply voltage of the pull - up resistor and iol shows the vol guarantee current. *2 : the maximum thddat only has to be met if the device does not extend the "l" width (tlow) of the scl signal. *3: tnft=(nfcr:nft[4:0]+1) x 2 x tclk_lcp0a note s: ? in this device, standard mode ( max. 100kbps ) is supported only. ? this model does not support h igh - speed mode. ( max. 400kbps ).
document number: 002 - 04863 rev.*d page 102 of 141 s6j31 2 0 series ? this model does not support min. i ol = 3ma with v ol = 0.4v. sd scl t hdsta t low t hddat t sudat t high t susta t hdsta t sp t buf t susto
document number: 002 - 04863 rev.*d page 103 of 141 s6j31 2 0 series 10.4.8 hs - spi timing 10.4.8.1 sdr mode timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) ( external load capacitance 16pf ) parameter symbol pin name conditions value unit remarks min max cycle time t cycm spiclk 2ma is selected in odr bit in ppc_pcfgr register. 62.5 - ns slave mode is not supported. clock high width t cwh spiclk 0.5 t cycm C cwl spiclk 0.5 t cycm C oslsksdr spiclk, spisel0 to spisel 3 1.5 t cycm C b spiclk end oskslsdr t cycm C osdatsdr spiclk, spidat0 to spidat3 - 10 10 ns spidat setup t dssetsdr spiclk, spidat0 to spidat3 " cmos schmitt input " and " disable noise filter " are selected in ppc_pcfgr register. 14 - ns spidat hold (mode0) t sdholdsd r0 0.5 t cycm - ns spidat hold (mode4) t sdholdsd r4 0 - ns
document number: 002 - 04863 rev.*d page 104 of 141 s6j31 2 0 series ? spi - i/f sdr mode 0 timing ? spi - i/f sdr mode 4 timing
document number: 002 - 04863 rev.*d page 105 of 141 s6j31 2 0 series 10.4.8.2 ddr mode timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) ( external load capacitance 16pf ) parameter symbol pin name conditions value unit remarks min max cycle time t cycm spiclk 2ma is selected in odr bit in ppc_pcfgr register. 62.5 - ns slave mode is not supported. clock high width t cwh spiclk 0.5 t cycm C cwl spiclk 0.5 t cycm C oslskddr spiclk, spisel0 to spisel 3 1.75 t cycm C b spiclk end oskslddr 0.75 t cycm C osdatddr spiclk, spidat0 to spidat3 0.25 t cycm C cycm + 10 ns spidat setup t dssetddr spiclk, spidat0 to spidat3 " cmos schmitt input " and " disable noise filter " are selected in ppc_pcfgr register. 14 - ns spidat hold (mode0) t sdholddd r 0 - ns
document number: 002 - 04863 rev.*d page 106 of 141 s6j31 2 0 series ? spi - i/f ddr mode 0 timing
document number: 002 - 04863 rev.*d page 107 of 141 s6j31 2 0 series 10.4.9 high current output s lew rate (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbo l pin name conditions value unit remarks min typ max output rise / fall time t r2 , t f2 p229 to p231, p300 to p302, p304 to p305, p307 to p309, p312 to p315, p317 - 15 - 100 ns load capacitance 85pf ? slew rate output timing v h v l v h v l t r2 t f2 v h =v ol2 +0.9 (v oh2 - v ol2 ) v l =v ol2 +0.1 (v oh2 - v ol2 )
document number: 002 - 04863 rev.*d page 108 of 141 s6j31 2 0 series 10.5 timer input timing (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name condition s value unit remarks min max input pulse width t twh , ? t twl tin0 to tin3, tin16 to tin19 - 4t clk_lcpna * - ns 4t clk_lcpna * 100 ns 100 4t clk_lcpna * <100 ns tin32 to tin33 - 4 t clk_ llpbm2 - ns 4 t clk_ llpbm2 100 ns 100 4 t clk_ llpbm2 <100 ns in0 to in11 - 4 t clk_lcp0a - ns 4 t clk_lcp0a 100 ns 100 4 t clk_lcp0a <100 ns text0 to 5 - 4 t clk_lcp0a - ns 4 t clk_lcp0a 100 ns 100 4 t clk_lcp0a <100 ns tioa0 to tioa29 tiob0 to tiob29 - 4 t clk_lcp0a - ns 4 t clk_lcp0a 100 ns 100 4 t clk_lcp0a <100 ns *: n=0:ch.0 to ch.3, n=1:ch.16 to ch.19 ? timer input timing v ih v il i n x t tiwl t tiwh v ih v il text x tioa x ,tiob x tin x
document number: 002 - 04863 rev.*d page 109 of 141 s6j31 2 0 series 10.6 qprc timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbo l pin name conditions value unit remarks min max ain pin "h" width t ahl ain8 to ain 9 - 4 t clk_lcp1 a - ns 4 t clk_lcp1 a all ain8 to ain 9 - bin pin "h" width t bhl bin8 to bin9 - bin pin "l" width t bll bin8 to bin9 - time from ain pin "h" level to bin rise t aubu ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_ m ode3 time from bin pin "h" level to ain fall t buad ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 time from ain pin "l" level to bin fall t adbd ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 time from bin pin "l" level to ain rise t bdau ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 time from bin pin "h" level to ain rise t buau ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 time from ain pin "h" level to bin fall t aubd ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 time from bin pin "l" level to ain fall t bdad ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 time from ain pin "l" level to bin rise t adbu ain8 to ain 9 , bin8 to bin 9 pc_mode2 or pc_mode3 zin pin "h" width t zhl zin8 to zin9 qcr:cgsc="0" zin pin "l" width t zll zin8 to zin 9 qcr:cgsc="0" time from determined zin level to ain/bin rise and fall t zabe ain8 to ain 9 , bin8 to bin 9 , zin8 to zin 9 qcr:cgsc="1" time from ain/bin rise and fall time to determined zin level t abez ain8 to ain 9 , bin8 to bin 9 , zin8 to zin 9 qcr:cgsc="1"
document number: 002 - 04863 rev.*d page 110 of 141 s6j31 2 0 series ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 04863 rev.*d page 111 of 141 s6j31 2 0 series zin ain/bin zin
document number: 002 - 04863 rev.*d page 112 of 141 s6j31 2 0 series 10.7 trigger input timing (t a : recommended operating conditions, vcc= dvcc= 5.0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name condition s value unit remarks min max input pulse width t trgh , t trgl int0 to int15 - 100 - ns int0 to int15 - 1 - s stop mode ? trigger input timing v ih v il intx t trgl t trgh v ih v il rxx
document number: 002 - 04863 rev.*d page 1 13 of 141 s6j31 2 0 series 10.8 nmi input timing (t a : recommended operating conditions, vcc=5. 0 v 10%, v ss =av ss =0.0 v) parameter symbo l pin name conditions value unit remarks min max input pulse width t nmil nmix - 3 00 - ns ? nmix input timing v ih nmix t n mil v ih v il v il
document number: 002 - 04863 rev.*d page 114 of 141 s6j31 2 0 series 10.9 low - voltage detection ( external low - voltage detection ) (t a : recommended operating conditions, v ss =av ss =0.0 v) parameter symbo l pin name condition s value unit remarks min typ max power s upply voltage range v dp5 vcc - 3.5 - 5. 5 v detection voltage v dl 0 vcc *1 *3 3.6 3.8 4. 0 v when power - supply voltage falls and detection level is set initially v dl1 vcc *1 *4 3.8 4.0 4.2 v v dl2 vcc *1 *5 4 4.2 4.4 v hysteresis width v hys vcc - - 100 - mv when power - supply voltage rises low - voltage detection time t d - - - - 30 s d ), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. *2 : please suppress the change of the power supply within the range of the power - supply voltage regulation to do a low - voltage detection by detecting voltage (v dl ) * 3: sysc0_runlvdcfgr.lvdh1v = 0100 b or sysc0_psslvdcfgr.lvdh1v = 0100 b * 4: sysc0_runlvdcfgr.lvdh1v = 0101 b or sysc0_psslvdcfgr.lvdh1v = 0101 b * 5: sysc0_runlvdcfgr.lvdh1v = 0110 b or sysc0_psslvdcfgr.lvdh1v = 0110 b
document number: 002 - 04863 rev.*d page 115 of 141 s6j31 2 0 series 10.10 low - voltage detection ( ram retention low - voltage detection ) (t a : recommended operating conditions, v ss =av ss =0.0 v) parameter symbol pin name condition s value unit remarks min typ max power s upply voltage range v rdp5 - - 0.6 - 1.4 v detection voltage * v rdl - * 1 0.9 0.95 1.0 v when power - supply voltage falls hysteresis width v rhys - - - 75 - mv when power - supply voltage rises low - voltage detection time t rd - - - - 30 s *: this lvd cannot be used to reliably generate a reset before voltage dips below minimum guaranteed mcu operation voltage, as this detection level is below the minimum guaranteed mcu operation voltage. * 1: if the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low - voltage detection time (t rd ), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. 10.11 low - voltage detection ( 1.2 v power supply low - voltage detection ) (t a : recommended operating conditions, v ss =av ss =0.0 v) parameter symbol pin name condition s value unit remarks guaranteed mcu operation range min typ max power s upply voltage range v rdp5 - - 0.6 - 1.4 v no detection voltage * v rdl 0 - * 1 *2 *4 0.92 0.97 1.02 v when power - supply voltage falls v rdl1 - *1 *3 *4 1.02 1.07 1.12 v hysteresis width v rhys - - - 75 - mv when power - supply voltage rises low - voltage detection time t rd - - - - 30 s *: this lvd cannot be used to reliably generate a reset before voltage dips below minimum guaranteed mcu operation voltage, as these detection levels are below the minimum guaranteed mcu operation voltage. * 1: if the fluctuation of the power supply has exceeded the detection voltage range within the time less than the low - voltage detection time (t rd ), there is the possibility to generate or release after the power supply voltage has exceeded the detection voltage range. * 2: sysc0_runlvdcfgr.lvdl1v = 10 b or sysc0_psslvdcfgr.lvdl1v = 10 b
document number: 002 - 04863 rev.*d page 116 of 141 s6j31 2 0 series * 3: sysc0_runlvdcfgr.lvdl1v = 11 b or sysc0_psslvdcfgr.lvdl1v = 11 b * 4 : these detection voltage level settings are below the minimum operation voltage. between these detection voltages and the minimum operation voltage, mcu functions are not guaranteed except for the low voltage detector. note that although the detection level is below the minimum operation voltage, the lvd reset factor flag is set as the voltag e drops below the detection level.
document number: 002 - 04863 rev.*d page 117 of 141 s6j31 2 0 series 10.12 a/d converter 10.12.1 electrical characteristics (t a : recommended operating conditions, vcc= dvcc= 5. 0 v 10%, v ss = dv ss = av ss =0.0 v) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit total error - - - - 12 lsb *3 integral nonlinearity - - - - 4.0 lsb *4 differential nonlinearity - - - - 1.9 lsb *4 zero transition voltage v z t *6 avrl - 11.5lsb - avrl +12.5lsb v *5 full - scale transition voltage v fst *6 avrh - 13.5lsb - avrh +10.5lsb v sampling time t smp - 0.3 - 12 s * 1 compare time t cmp - 0.7 - 28 s * 1 a/d conversion time t cnv - 1.0 - 40 s * 1 analog port input current i ain * 7 - 1.0 - 1.0 a v avss v ain v avcc *8 - 2.0 - 2.0 *9 - 3.0 - 3.0 analog input voltage v ain *6 avss - avrh v reference voltage avrh avrh 0,avrh 1 4.5 - 5. 5 v avcc avrh avrl avrl 0/avss 0,avrl1/avs s1 - 0.0 - v power supply current i a avcc - 500 900 a per one unit i ah - 1.0 100 a *2 i r avrh - 1 2 ma per one unit i rh - - 5.0 a * 2 variation between channels - * 10 - - 4 lsb an32 to an43, an46 to an53, an55 to an62 - - 4 lsb *1 : time for each channel *2 : the power supply current (v cc =av cc =5.0v) is specified if the a/d converter is not operating and cpu is stopped. * 3 : total error is a comprehensive static error that includes the linearity . 1lsb=( avrh - avr l)/4096 * 4 : 1lsb=(v fst - v zt )/4094 * 5 : 1lsb=( a v r h - a vrl)/4096 *6: an3, an5, an6, an9, an10, an12 to an15, an17 to an24, an27 to an 43 , an 46 to an 53 , and an 55 to an 62 *7: an3, an5, an6, an9, an10, an12 to an15, an17 to an24, and an27 to an42
document number: 002 - 04863 rev.*d page 118 of 141 s6j31 2 0 series *8: an0 to an2, and an43 *9: an44 to an62 * 10 : an3, an5, an6, an9, an10, an12 to an15, an17 to an24, and an27 to an31
document number: 002 - 04863 rev.*d page 119 of 141 s6j31 2 0 series 10.12.2 notes on using a/d converters about the output impedance of an external circuit for analog input when the external impedance is too high, the analog voltage sampling time may become insufficient. in this case, we recommend attaching a capacitor (about 0.1 f) to an analog input pin. analog input circuit model rint : analog input impedance 3.9 kiloohms (max) (4.5 v avcc 5.5 v) cint : capacitance of mcu input pin 11.0pf (max) (4.5 v avcc 5.5 v ) rext : external driving impedance cext : capacitance of pcb at a/d converter input the following approximation formula for the replacement model above can be used: sampling time (minimum) = 9 x ( ( rin + rext ) x cin + rext x cext ) note: listed values must be considered as reference values. source cext cint rint r ext analog input comparator
document number: 002 - 04863 rev.*d page 120 of 141 s6j31 2 0 series 10.12.3 definition of terms resolution: analog variation that is recognized by an a/d converter integral nonlinearity error * : deviation of the straight line connecting the zero transition point ("0000 0000 0000" < -- > "0000 0000 0001") and full - scale transition point ("1111 1111 1110" < -- > "1111 1111 1111") from actual conversion characteristics includes zero transition error, full - scale transition error, and non - linearity error . differential nonlinearity error : deviation from the ideal value of the input voltage required for changing the output code by 1 lsb total error: difference between the actual value and the theoretical value. the total error includes zero transition error, full - scale transition error, and non linearity error. *: represented as "linearity error" in the former product series. total error total error of digital output n = v nt - {1 lsb (n - 1) + 0.5lsb } [lsb] 1lsb 1lsb (ideal value) = a v rh - a v rl [v] 409 6 n : a/d converter digital output value. v zt ( ideal value) = avrl + 0.5lsb[v] v fs t ( ideal value) = avrh - 1.5lsb[v] v n t : voltage at which the digital output changes from " (n C 1) " to " n ". fff ffe ffd 004 003 002 001 a v rl (a v ss ) avrh {1 lsb (n - 1) + 0.5lsb } 1.5lsb v nt 0.5lsb ideal characteristics actual conversion characteristics ( actually - measured value) analog input actual conversion characteristics (measured value) digital output
document number: 002 - 04863 rev.*d page 121 of 141 s6j31 2 0 series integral nonlinearity differential nonlinearity integral nonlinearity of digital output n = v nt - {1 lsb (n - 1) + v zt } [lsb] 1lsb differential nonlinearity of digital output n = v (n+1) t - v nt - 1 lsb [lsb] 1lsb 1lsb = v fst - v zt [v] 4094 v zt : voltage for which digital output changes from "0x000" to "0x001" v fst : voltage for which digital output changes from "0xffe" to "0xfff". fff ffe ffd 004 003 002 001 a vss ( a vrl) avrh avrh actual conversion characteristics {1 lsb (n - 1) + v zt } n - 1 a vss ( a vrl) n - 2 n n + 1 v fst v nt v zt v (n+1)t v nt ideal characteristics actual conversion characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output ( actually - measured value) ( actually - measured value) ( actually - measured value) ( actually - measured value) analog input analog input (actually - measured value) (measured value) digital output
document number: 002 - 04863 rev.*d page 122 of 141 s6j31 2 0 series 10.13 flash memory parameter rating unit remarks min typ max sector erase time - 300 1100 ms 8 - kb sector *1 internal preprogramming time included - 800 3700 ms 64 - kb sector *1 internal preprogramming time included 8 - bit write time - 15 288 s system - level overhead time excluded *1 16 - bit write time - 19 384 s system - level overhead time excluded *1 32 - bit write time - 27 567 s system - level overhead time excluded *1 64 - bit write time - 45 945 s system - level overhead time excluded *1 8 - bit (with ecc) write time - 19 384 s system - level overhead time excluded *1 16 - bit (with ecc) write time - 23 483 s system - level overhead time excluded *1 32 - bit (with ecc) write time - 31 651 s system - level overhead time excluded *1 64 - bit (with ecc) write time - 49 1029 s system - level overhead time excluded *1 erase count *2 / data retention time 1,000/20 years, 10,000/10 years, 100,000/5 years - - - temperature at write/erase time average temperature t a =+85 degrees celsius *1 : guaranteed value for up to 100,000 erases *2 : number of erases for each sector note s : ? while the flash memory is written or erased, shutdown of the external power (vcc) is prohibited. ? in the application system where vcc might be shut down while writing or erasing, be sure to turn the power off by using an external low - voltage detection function. ? to put it concretely, after the external power supply voltage falls below the detection voltage (v dl ), hold vcc at 2.7v or more within the duration calculated by the following expression: t d * 1 [s] + (1 / f crf * 2 [mhz]) x 1029 + 25 [s] *1 : see "12.8 low - voltage detection (external low - voltage detection)" *2 : see "12.4.1 source clock timing"
document number: 002 - 04863 rev.*d page 123 of 141 s6j31 2 0 series 11. o rdering i nformation part number package s6j31 2xh z c s e y 0000 * 144 - pin plastic, teqfp( leu144 ) note: ? "x" / " y " is an part number option. for the part number option, see the following table. for details on each package, see " package dimensions ." * z: a/b 12. p art n umber o ption part number option " x " flash memory a 1mbyte 9 768kbyte 8 512kbyte part number option " y " 1 sn - bi & halogen free 2 puresn & halogen free part number option z she a she on b she off
document number: 002 - 04863 rev.*d page 124 of 141 s6j31 2 0 series 13. p ackage d imensions package type package code ex - lqfp 144 l eu144 002 - 10858 ** n o t e s : r e f l 1 l c d i m e nsion s n om . m i n . s y m b o l m ax . 0 . 1 2 0 . 2 0 0 . 4 5 0 . 6 0 0 . 7 5 1 . 0 0 0 . 2 5 b s c b s c b s c b s c d i m e nsion s n om . m i n . d 1 e 1 e d a 2 a a 1 s y m b o l m ax . 1 . 7 0 0 . 0 0 0 . 2 0 1 . 3 5 1 . 4 0 1 . 4 5 2 2 . 0 0 2 0 . 0 0 2 2 . 0 0 2 0 . 0 0 0 . 1 7 0 . 2 7 b e 0 . 2 2 b sc . 0 . 5 0 1 r r 2 0 . 0 8 0 . 2 0 0 . 0 8 0 4 8 d 2 d 3 b s c 7 . 0 5 b s c 5 . 8 5 e 2 e 3 b s c 7 . 0 5 b s c 5 . 8 5 1 . a ll d i m e n s ions a r e i n mi l l i m ete r s . 2 . datum p l ane h i s lo c a t e d at t h e bottom of t h e m o l d p a r t i n g line c o in c i de n t w i t h w h e r e t h e l e a d ex i ts t h e b o d y. 3 . d a tum s a - b a n d d t o b e de t erm i n e d at d at u m pla n e h . 4 . t o b e det e r m i n ed a t s e at i n g pla n e c . 5 . d i m e n s i o n s d 1 a n d e 1 d o n o t i n c l u d e m o l d p r o t ru s i o n . al l o w a bl e pr o tr u s i o n is 0. 2 5 mm pre si d e. d i m e n s i o n s d 1 a n d e 1 i n c l u d e m o l d m i s m a t c h a n d a r e d ete rm i n e d at d a t u m pl a n e h . 6 . det a il s o f p i n 1 ide n t i f i e r a r e o p tio n a l but m u s t b e l o c ated w i t h i n t h e z o n e i nd i c ate d . 7 . re g a rd l es s o f the rel a ti v e s i z e o f the upp e r a nd l o w e r b o d y s e c t i o n s . d i m e n s i o n s d 1 a nd e 1 a r e d e te r m i n e d at t h e l a rg est f ea t ur e o f the b o d y e x c l usi v e of m o ld f l ash an d gat e bu rr s. but in c l u d in g any m i sm a t c h b e t w e en t h e u ppe r a nd l o w er s e c t io n s of t h e mo l d e r bo d y. 8 . d i m e n s i o n b d o e s n o t i n c l u d e d a m b e r p r o t r u s i on . t h e d a m bar pr o t r u s i o n ( s ) sha l l n o t c a u s e the l e ad wi d t h t o ex c ee d b m a x i m um b y m o re than 0 . 0 8 mm . dam b a r c a nn o t be l o c ate d o n t h e l o w e r r adi u s o r the l ead fo o t. 9 . e xact s h a p e a nd si z e of t h i s f e atu r e is o pti o n al. 1 0 . t h e se d i me n s i o ns a pp l y t o t h e fl a t s e c t i o n o f t h e lead b e tw e e n 0. 1 0 m m an d 0 .2 5 mm f r om t h e lea d tip . 1 1 . a1 is d e f i n e d a s t h e d i s tan c e f r om t h e se a tin g pla n e to the l o w e st p o i n t o f t h e p a c ka g e b o d y. l 2 4 5 7 0.2 0 c a - b d 0.1 0 c a - b d 2 1 1 deta i l a 0.0 8 c s e a t i n g p l an e 0.0 8 c a - b d 8 s i d e vie w t o p vie w b o t t o m vie w 1 0 g a u g e p l a n e deta i l a d 1 d d 2 d 3 e 1 e e 3 e 2 e xposed pad r 2 r 1 b l l1 l2 a 2 a 1 a e c package ou t line, 1 44 le a d t e q fp 20 . 0x20 . 0x1 . 7 m m le u 144 r ev * *
document number: 002 - 04863 rev.*d page 125 of 141 s6j31 2 0 series 14. appendix 14.1 application 1: jtag tool connection this is an application example of jtag tool connection. * x: a/9/8 s6j312 xh (144pin) * trst arm jtag 20 gnd r +5v r +5v r gnd gnd r r tdi tms tck tdo rstx 112 113 114 111 123 110 r vss r vcc r vcc r vcc r vcc ntrst tdi tms tck tdo nsrst rtck vtref dbgrq dbgack gnd gnd gnd gnd gnd gnd gnd nc gnd gnd 3 5 7 9 13 15 11 1 17 19 4 6 8 10 14 16 12 2 18 20
document number: 002 - 04863 rev.*d page 126 of 141 s6j31 2 0 series 15. m ajor c hanges page section change results revision *a 1 features cortex - r5 core revised the following note . (error) ? ecc s upport for the tcm ports (correct) ? ecc support for the tcm ports for ram 1 features peripheral functions revised the full productio n and she - off series as follows . (correct) ? built - in flash memory size ? program: 1024 k + 64 kb (s6j312ahzb*)/768 k + 64 kb (s6j3129hzb*)/512 k + 64 kb (s6j3128hzb*) ? *z: a/b ? work: 112 kb (s6j312ahzb*)/ 112 kb (s6j3129hzb*)/112 kb (s6j3128hzb*) ? *z: a/b 1 features peripheral functions revised the full productio n and she - off series as follows . (correct) ? built - in ram size ? tcram 64 kb(s6j312ahzb*)/ 48 kb(s6j3129hzb*)/32 kb(s6j3128hzb*) ? system sram 16 kb (s6j312ahzb*)/ 16 kb (s6j3129hzb*)/ 16 kb (s6j3128hzb*) ? backup ram 8 kb (s6j312ahzb*)/ 8 kb (s6j3129hzb*)/8 kb (s6j3128hzb*) ? *z: a/b 1 features peripheral functions revised the full productio n and she - off series as follows . (correct) ? general - purpose ports: 112 channels (s6j312ahzb*)/ 112 channels (s6j3129hzb*)/ 112 channels (s6j3128hzb*) ? *z: a/b 1 features peripheral functions revised the full productio n and she - off series as follows . (correct) ? a/d converter (successive approximation type) ? 12 - bit resolution, 2 units mounted: max 50 channels (22 channels + 28 channels)(s6j312ahzb*)/ max 50 channels (22 channels + 28 channels)(s6j3129hzb*)/ max 50 channels (22 channels + 28 channels)(s6j3128hzb*) ? *z: a/b 1 features peripheral functions revised the full productio n and she - off series as follows . (correct) ? multi - function serial (transmission and reception fifos mounted) :max 10 channels(s6j312ahzb*)/ max 10 channels(s6j3129hzb*)/ max 10 channels(s6j3128hzb*) ? *z: a/b 1 features peripheral functions add ed the following function lists. ? full duplex, double buffering system; 64 - byte transmission fifo, 64 - byte reception fifo ? standard mode (max. 100kbps) is supported only. ? dma transfer is supported. 2 features peripheral functions revised the following function list. (error) ? can transfer speed : 1 mbps (correct) ? can transfer speed : 5 mbps
document number: 002 - 04863 rev.*d page 127 of 141 s6j31 2 0 series page section change results 2 features peripheral functions added the following function list under can controller. ? 32 message buffer/channel (transmission message buffer size) 2 features peripheral functions added the following function list under low - power consumption. ? partial wakeup function 2 features peripheral functions revised the follows as full production. (correct) ? package: leu144 (s6j312xhzb*) ? *x:a/9/8, z: a/b 6 1 . product lineup added table 3 - 1 memory size as full production. 6 1 . product lineup added table 3 - 2 she option as full production. 6 1 . product lineup added full production and notes as follows. * 1 : x: a/9/8, z: a/b * 2 : i 2 c - uart function is not supported at multi - function serial ch.1, ch.2, and ch.12. 6 1 . product lineup revised the following frequency. (correct) maximum cpu operating frequency : 128 mhz 7 1 . product lineup added the following function list under low - power consumption. ? partial wakeup function 8 2 . pin assignment revised figure 4 - 1 pin assignment for s6j31 2 xhzb* as follows. (correct) * x: a/9/8, z: a/b 9 3 . p in d escription revised the tables as follows for full production. (correct) table 5 - 1 s6j31 2 xhzb* pin functions * x: a/9/8, z: a/b
document number: 002 - 04863 rev.*d page 128 of 141 s6j31 2 0 series page section change results 1 0 ,1 1 ,1 2 ,1 5 , 16 , 17 , 18 , 2 0 , 21 , 24 3 . p in d escription revised the i/o pin to output pin as follows (correct) pin 13 multi - function serial ch.11 serial chip select 1 output pin (0) pin14 multi - function serial ch.11 serial chip select 2 output pin (0) pin 15 multi - function serial ch.11 serial chip select 3 output pin (0) pin 23 multi - function serial ch.4 serial chip selec t 2 output pin (1) pin 26 multi - function serial ch.4 serial chip select 3 output pin (1) pin 49 multi - function serial ch.9 serial chip select 1 output pin (0) pin 50 multi - function serial ch.9 serial chip select 2 output pin (0) pin 51 multi - function seria l ch.9 serial chip select 3 output pin (0) pin 62 multi - function serial ch.4 serial chip select 3 output pin (0) pin 64 multi - function serial ch.4 serial chip select 2 output pin (0) pin 68 multi - function serial ch.4 serial chip select 1 output pin (0) pin 76 multi - function serial ch.8 serial chip select 3 output pin (0) pin 78 multi - function serial ch.8 serial chip select 1 output pin (0) pin 97 multi - function serial ch.10 serial chip select 2 output pin (0) pin 100 multi - function serial ch.10 serial ch ip select 1 output pin (0) pin 136 multi - function serial ch.10 serial chip select 1 output pin (1) pin 137 multi - function serial ch.10 serial chip select 3 output pin (1) 19 3 . p in d escription deleted pin87 rx0_1 from table 5 - 1 s6j312xhzb* pin functions (error) 87 p229 int8_0 an46 pwu_an6 rx0_1 out0_0 tioa25_0 pwm1p0 - - - - - - - - m general - purpose i/o port int8 external interrupt input pin (0) adc analog 46 input pin partial wakeup adc analog 6 input pin can reception data 0 input pin (1) output compare ch.0 output pin (0) base timer ch.25 tioa i/o pin (0) smc ch.0 (p1) output pin (correct) 87 p229 int8_0 an46 pwu_an6 out0_0 tioa25_0 pwm1p0 - - - - - - - m general - purpose i/o port int8 external interrupt input pin (0) adc analog 46 input pin partial wakeup adc analog 6 input pin output compare ch.0 output pin (0) base timer ch.25 tioa i/o pin (0) smc ch.0 (p1) output pin
document number: 002 - 04863 rev.*d page 129 of 141 s6j31 2 0 series page section change results 2 0 3 . p in d escription deleted pin97 rx0_0 from table 5 - 1 s6j312xhzb* pin functions (error) 97 p307 int1_0 an55 rx0_0 scs102_0 tiob18_0 pwm1p2 - - - - - - - m general - purpose i/o port int1 external interrupt input pin (0) adc analog 55 input pin can reception data 0 input pin (0) multi - function serial ch.10 serial chip select 2 i/o pin (0) base timer ch.18 tiob input pin (0) smc ch.2 (p1) output pin (correct) 97 p307 int1_0 an55 scs102_0 tiob18_0 pwm1p2 - - - - - - m general - purpose i/o port int1 external interrupt input pin (0) adc analog 55 input pin multi - function serial ch.10 serial chip select 2 output pin (0) base timer ch.18 tiob input pin (0) smc ch.2 (p1) output pin 9 ,1 0 ,1 1 , 15 , 16 , 17 , 19, 2 1 3 . p in d escription added the i2c function to pin 6,7,10,11,18,19,57,58,63,65,80,81,101,102 pin 6 sda3_0 i 2 c bus ch.3 serial data i/o pin pin 7 scl3_0 i 2 c bus ch.3 serial clock i/o pin pin 1 0 sda 11 _0 i 2 c bus ch. 11 serial data i/o pin pin 1 1 scl 11 _0 i 2 c bus ch. 11 serial clock i/o pin pin 18 sda 0 _0 i 2 c bus ch. 0 serial data i/o pin pin 19 scl 0 _0 i 2 c bus ch. 0 serial clock i/o pin pin 57 sda 9 _0 i 2 c bus ch. 9 serial data i/o pin pin 58 scl 9 _0 i 2 c bus ch. 9 serial clock i/o pin pin 63 sda 4 _0 i 2 c bus ch. 4 serial data i/o pin pin 65 scl 4 _0 i 2 c bus ch. 4 serial clock i/o pin pin 80 sda 8 _0 i 2 c b us ch. 8 serial data i/o pin pin 81 scl 8 _0 i 2 c bus ch. 8 serial clock i/o pin pin 1 01 sda 10 _0 i 2 c bus ch. 10 serial data i/o pin pin 1 02 scl 10 _0 i 2 c bus ch. 10 serial clock i/o pin 18 , 19 3 . p in d escription added the partial wakeup adc analog input to pin 78 ,79,80,81,87,88 . pin78 pwu_an0 partial wakeup adc analog 0 input pin pin7 9 pwu_an 1 partial wakeup adc analog 1 input pin pin 80 pwu_an 2 partial wakeup adc analog 2 input pin pin 81 pwu_an 3 partial wakeup adc analog 3 input pin pin 87 pwu_an 6 partial wakeup adc analog 6 input pin pin 88 pwu_an 7 partial wakeup adc analog 7 input pin 2 1 3 . p in d escription added the partial wakeup trigger output to pin 107. pin107 pwutrg partial wakeup trigger output pin 19 , 2 0 , 2 3 3 . p in d escription deleted the following function on each pins. p i n 87 rx0_1 can reception data 0 input pin (1) pin 97 rx0_0 can reception data 0 input pin (0) pin131 rx2_1 can reception data 2 output pin (1) pin132 tx2_1 can transmission data 2 output pin (1)
document number: 002 - 04863 rev.*d page 130 of 141 s6j31 2 0 series page section change results 27 4 . i/o circuit types revised type c of i/o circuit type as follows: (correct) 3 0 4 . i/o circuit types added type r to 11. i/o circuit type r output o f 2 ma 37 6 . handling devices revised the vss pin in figure 8 - 1 pin assignment. (correct) 38 6 . handling devices revised the items as follows. (correct) this device has a built - in voltage step - down circuit. be sure to connect a capacitor to the c pin (pin 126 in s6j312xhzb* specifications) for internal stabilization of the device. for the standard values, see "recommended operating conditions" in the latest data sheet. * x:a/9/8, z: a/b 39 7 . block diagram revised the title as follows. (correct) figure 9 - 1 s6j312xhzb* block diagram *x: a/9/8, z: a/b 39 7 . block diagram added partial wake up to block diagram mode input digital output digital output
document number: 002 - 04863 rev.*d page 131 of 141 s6j31 2 0 series page section change results 4 0 8 . memory map revised figure 10 - 1 memory map as full production. (correct) 4 1 8 . memory map a dded item as follows. the ecc movement in tcm port is based on ecc setting inside the cpu. 4 1 8 . memory map revised " s6j31 2 xh aa peripheral map " as follows (correct) s6j31 2 xhzb* peripheral map * x:a/9/8, z:a/b
document number: 002 - 04863 rev.*d page 132 of 141 s6j31 2 0 series page section change results 4 5 8 . memory map added p artial wake up to address of b484_8400 to b484_87ff . b484_8400 b484_87ff apps #5 a/d unit1 , partial wake up 297 4 5 8 . memory map revised the memory map of apps#5 as follows. (correct) b484_8c00 b484_8fff reserved - b484_9000 b484_93ff apps #5 global timer 300 b484_9400 b484_ffff reserved - 45 8. memory map revised the memory map of apps# 7 as follows. (correct) start address end address function ppu no b48c_0000 b48c_3fff reserved - b48c_4000 b48c_43ff apps #7 stepper motor control ch.0 317 b48c_4400 b48c_47ff apps #7 stepper motor control ch.1 318 b48c_4800 b48c_4bff apps #7 stepper motor control ch.2 319 b48c_4c00 b48c_4fff apps #7 stepper motor control ch.3 320 b48c_5000 b48c_57ff reserved - b48c_5800 b48c_5bff apps #7 smc trigger generator 323 b48c_5c00 b48c_5fff apps #7 liquid crystal display controller 324 b48c_6000 b48c_63ff apps #7 liquid crystal display input/output control 325 b48c_6400 b48c_ffff reserved - 4 5 8 . memory map added the following note. when mpu attribute of cortex? - r5 is configured as "normal", store buffer inside cortex? - r5 can operate and write data can be merged. to avoid influence of this data merger, mpu attribute "device" or "strongly ordered" should be used. mpu attribute "device" or "strongly ordered" must be used for areas below, to avoid this influence. ? backup ram area (backup_ram) [0e80_0000 ~ 0e87_ffff] ? peripheral area (peri area) [b000_0000 ~ b7ff_ffff] ? error config area (errcfg) [fffe_e000 ~ fffe_ffff] mpu attribute "device" or "strongly ordered" is required for accesses to areas below, in particular situation. ? flash memory (when writing commands) 4 5 8 . memory map added the following note. she off product is prohibited to access she area (b200_0000 to b20f_ffff) 46 , 47 9 . p in s tatus in cpu s tatus added pin name about i 2 c and pwu to table 11 - 1 pin state table (1/2) and table 11 - 2 pin state table (2/2) . 47 9 . pin status in cpu status deleted the following pin name about canfd ch2 from table 11 - 2 pin state table (2/2) pin132 : tx2_1 pin131 : rx2_1 pin87 : rx0_1 pin97 : rx0_0 48 9 . p in s tatus in cpu s tatus added the item as follows *7: when the pwu function is enabled, a change to output occurs. *8: when ppc_pcfgrijj:pof[2:0] is set to initial value. *9: when reset is issued, the following ports become "l" output as the initial state.
document number: 002 - 04863 rev.*d page 133 of 141 s6j31 2 0 series page section change results 5 0 1 0 . e lectrical c har acteristics 1 0 .1 absolute maximum ratings revised the remarks of analog supply voltage (error) av cc v cc (correct) a v cc = v cc 5 0 1 0 . e lectrical c haracteristics 1 0 .1 absolute maximum ratings revised the symbol of maximum clamp current . (error) i clamp (correct) | i clamp | 5 0 1 0 . e lectrical c haracteristics 1 0 .1 absolute maximum ratings revised the following note. (error) *2: vcc and dvcc must be set to the same voltage. caution must be taken that avcc and dvcc does not exceed vcc upon power - on and under other circumstances. (correct) *2: avcc, dvcc and vcc must be set to the same voltage. it is required that avcc and dvcc do not exceed vcc and that the voltage at the analog inputs does not exceed avcc when the power is switched on. 5 2 1 0 . e lectrical c har acteristics 1 0 .2 recommended operating conditions revised the following title. (error) rating (correct) value 5 2 1 0 . e lectrical c haracteristics 1 0 .2 recommended operating conditions revised the parameter of smoothing capacitor as follows. (correct) smoothing capacitor * c s1 4.7 f tolerance of up to 40% , 126pin use a ceramic capacitor or a capacitor that has the similar frequency characteristics. use a capacitor with a capacitance greater than cs as the smoothing capacitor on the vcc pin. 5 2 1 0 . e lectrical c haracteristics 1 0 .2 recommended operating conditions revised the remarks of operating temperature as follows. (error) s6j312haa (correct) s6j312xhzb* * x:a/9/8, z:a/b 5 2 1 0 . e lectrical c haracteristics 1 0 .2 recommended operating conditions revised the following diagram (correct) ? c pin connection diagram c s 1 c (126pin) v ss av ss v ss c (38pin) open
document number: 002 - 04863 rev.*d page 134 of 14 1 s6j31 2 0 series page section change results 5 3 1 0 . electrical characteristics 1 0 .2 recommended operating conditions added the following notes. notes: ? the following condition should be satisfied in order to facilitate heat dissipation. 1. 4 or more layers pcb should be used. 2. the area of pcb should be 114.3 mm x 76.2 mm or more, and the thickness should be 1.6 mm or more. (jedec standard) 3. 1 layer of middle layers at least should be used for dedi cated layer to radiate heat with residual copper rate 90% or more. the layer can be used for system ground. 4. 35~50% of the die stage area which is exposed at back surface of package should be soldered to a part of 1st layer. 5. the part of 1st layer shou ld be connected to the dedicated heat radiation layer with more than 10 thermal via holes. 5 3 ,5 4 1 0 . electrical characteristics 1 0 .2 recommended operating conditions added the following notes and figures. figure12.2 - 1: example thermal via holes on pcb. notes: ? figure 12.2 - 1 is a schematic diagram showing pcb in section. ? figure 12.2 - 2 in the following pages are recommended land patterns for each package series. thermal via holes should closely be placed and aligned with lands. ? if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. figure 12.2 - 2: land pattern and thermal via leu144 6 3 1 0 . electrical characteristics 1 0 .3 dc characteristics revised the following pins of rup3 (e rror) p321 , tdi(p324), tms,tck (correct) tdi(p324), tms,tck 6 5 1 0 . electrical characteristics 1 0 .3 dc characteristics revised the following values and remarks. i cc5 ,i ccs5 :remarks (error) operating at 112 mhz (correct) operating at 128 mhz i cc5 : value (error) normal operation | typ 100ma | max 225ma (correct) normal operation | typ 90 ma | max 195 ma icct52:value (error) max 115 a (correct) max 100 a icct52 m :value (error) typ 700 a | max 885 a (correct) typ 350 a | max 520 a icc h 52:value (error) max 110 a (correct) max 100 a 6 5 1 0 . electrical characteristics 1 0 .3 dc characteristics added the following characteristic icc p | pwu mode( shutdown )
document number: 002 - 04863 rev.*d page 135 of 141 s6j31 2 0 series page section change results 6 5 1 0 . electrical characteristics 1 0 .3 dc characteristics revised the followings in parameter cell. (error) s6j312haa (correct) s6j312xhzb* *x:a/9/8 z: a/b 69 1 0 . electrical characteristics 1 0 .4.2 internal clock timing revised the value of frequency excepts f clk_extbus and f canfd_cclk (correct)
document number: 002 - 04863 rev.*d page 136 of 141 s6j31 2 0 series page section change results 7 0 1 0 . electrical characteristics 1 0 .4.2 internal clock timing revised the value of pulse width excepts t clk_extbus and t canfd_cclk (correct) 7 1 1 0 . electrical characteristics 1 0 .4.2 internal clock timing revised the value of max internal frequency f cpu_clk in guaranteed operation range (error) 112mhz (correct) 128 mhz 7 2 1 0 . electrical characteristics 1 0 .4.2 internal clock timing revised the followings relationship between the oscillation clock frequency and internal clock frequency pll multiplier setting (error) 112 (correct) 128 pll clock (error) 112mhz (correct) 128 mhz notes (error) the maximum pll clock frequency must be 1 1 2mhz. (correct) the maximum pll clock frequency must be 128 mhz. 7 4 1 0 . electrical characteristics 1 0 .4.4 power - on conditions added the parameter of level release voltage
document number: 002 - 04863 rev.*d page 137 of 141 s6j31 2 0 series page section change results 7 4 1 0 . electrical characteristics 1 0 .4.4 power - on conditions revised the value of level detection voltage (error) min 2.25v | typ 2.45v | max 2.65v (correct) min 2.15 v | typ 2.35 v | max 2.55 v 10 1 ,10 2 1 0 . electrical characteristics 1 0 .4.7.4 i 2 c timing (smr:md[2:0]=100b) added the characteristic of i 2 c timing (smr:md[2:0]=100b) 11 6 ,11 7 1 0 . electrical characteristics 1 0 .12 a/d converter 1 0 .12.1 electrical characteristics revised the value of analog port input current in the table, and revised the pin name note *7 to *9 (correct) *7: an3, an5, an6, an9, an10, an12 to an15, an17 to an24, and an27 to an42 *8: an0 to an2, and an43 *9: an44 to an62 1 19 1 0 . electrical characteristics 1 0 .12 a/d converter 1 0 .12.3 definition of terms revised the followings. (error) total error: difference between the actual value and the theoretical value. the total error (correct) total error: difference between the actual value and the theoretical value. the total error includes zero transition error, full - scale transition error, and non linearity error. 12 1 1 0 . electrical characteristics 1 0 .13 flash memory deleted the followings. *3: target value 12 2 1 1 . o rdering i nformation added she option to the part number part number option z she a she on b she off 12 2 1 2 .part number option added flash memory size option to the part number . part number option " x " flash memory a 1mbyte 9 768kbyte 8 512kbyte revision *b 1 cover revised the title as follow (error) S6J3120 series 32 - bit microcontroller spansion? traveo? family (correct) S6J3120 series 32 - bit traveo? family microcontroller datasheet 2 features added can - fd (v3.2.0) under can controller: can - fd max 3 channel. 37 6 . h andling devices revised the following notice. (error) about the power - on time to prevent the internal built - in voltage step - down circuit from malfunctioning, secure a voltage rising time of 50 s (between 0.2 v and 2.7 v) or longer at the power - on time. (correct) about the p ower - on t ime to prevent a malfunction of the voltage step - down circuit built in the device, the voltage rising must be monotonic during power - on.
document number: 002 - 04863 rev.*d page 138 of 141 s6j31 2 0 series page section change results 70 10. electrical characteristics 10.4.2 internal clock timing revised the following symbol. (error) tclk_fma (correct) tclk_ d ma 74 10. electrical characteristics 10.4.4 power - on conditions deleted the slope detection undetected specification. added the power ramp rate and maximum ramp rate guaranteed to not generate power - on reset . *1, *2: changed the sentence. added *3, *4, note, fig ure at the power off time, power ramp rate, maximum ramp rate guaranteed to no t generate power - on reset . 101 10. electrical characteristics 10.4.7.4 i2c timing (smr:md[2:0]=100b) revised the following pin names. (error) scl0 to scl4 / sda0 to sda4 (correct) scl0, scl3, scl4 / sda0, sda3, sda4 115 10. electrical characteristics 10. 10 low - voltage detection (ram retention low - voltage detection) revised the title in 10. 10 internal low - voltage detection to ram retention low - voltage detection . 115 10. electrical characteristics 10.11 low - voltage detection (1.2 v power supply low - voltage detection) added the notice *4 123 11. ordering information revised the following part number. (error) s6j312xhzbasey0000* (correct) s6j312xhz c sey0000* 1,2,6 to 9, 38 to 40, 42,50,52, 65,69,70, 74,123 - revised part number from s6j31 2 xxxb to s6j31 2 xxxc. note: please see document history about later revised information.
document number: 002 - 04863 rev.*d page 139 of 141 s6j31 2 0 series document history document title: S6J3120 series 32 - bit traveo? family microcontroller datasheet document number: 002 - 04863 revision ecn orig. of change submission date description of change ** - hiha 8 / 7 /201 4 initial release new spec. *a 4993737 wecu 10/ 29 /2015 added full product names. added 144pin pwutrg function. added simultaneous function for start timing of pwm does not overlap. added i2c function. added she - off option. updated canfd macro (updated to v3.2.0). revised min value of vih6 (trst tck tdi tms) from2.0v to 2.3v. revised operating frequency to 128mhz, and revised clock frequency based 128mhz. revised current consumption standard (icc5 icct52 icct52m icch52). added partial wakeup macro. for detail, see major changes. *b 5309249 wecu 06/1 6 /2016 revised part number from s6j311xxxb to s6j311xxxc. for detail, see major changes. *c 5375465 wecu 07/2 7 /2016 page74, 10.4.4 power - on conditions revised level detection time from 30 to 540, revised *1 to *4 and note. page115, 10.10 low - voltage detection (ram retention low - voltage detection) added * and note to detection voltage. page115, 10.11 low - voltage detection (1.2 v power supply low - voltage detection) added * and note to detection voltage.
document number: 002 - 04863 rev.*d page 140 of 141 s6j31 2 0 series revision ecn orig. of change submission date description of change *d 5 554888 wecu 12/1 5 /2016 page 124, replaced 13. package dimensions page 125 , added 14.appendix
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